Advances in semiconductor technology coupled with the increasing availability of soft and hard IP libraries enable embedded system designers to develop Systemson-Chip (SOCs) containing highly customized processors and memories for their specific applications. However, there is a strong demand for a methodology and tools that support efficient Design Space Exploration (DSE) of SOC architectures. Architecture Description Language (ADL)-based SOC codesign is a promising approach to efficient DSE of SOC architectures. ADLs are languages designed for specification of SOC architecture templates, and are used to perform early validation of SOC architectures, as well as to automatically generate software toolkits required to complete the integrated, and concurrent hardware and software design of the SOCs. In this paper we survey recent efforts in the use of ADLs. We conclude with a discussion of several major challenges facing ADL-based codesign of future SOCs. 1.
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97
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EXPRESSION: A language for Architecture exploration through compiler/simulator retargetability
– Halambi
- 1999
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78
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ISDL: An instruction set description language for retargetability
– Hadjiyiannis, Hanono
- 1997
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62
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Describing instruction set processors using nML
– Fauth, Praet, et al.
- 1995
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55
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Retargetable Code Generation for Digital Signal Processors
– Leupers
- 1997
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54
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Specifying representation of machine instructions
– Ramsey, Fernindez
- 1997
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44
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Instruction Selection, Resource Allocation, and Scheduling
– Hanono, Devadas
- 1998
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43
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The nml machine description formalism
– Freericks
- 1993
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43
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Flexware: A flexible firmware development environment for embedded systems
– Paulin, Liem, et al.
- 1995
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37
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Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems
– Leupers, Marwedel
- 1998
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37
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A machine description language for compilation
– Gyllenhaal
- 1994
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37
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LISAmachine description language for cycle-accurate models of programmable DSP architectures
– Pees, Hoffmann, et al.
- 1999
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34
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Lisa - machine description language and generic machine model for hw/sw co-design
– Zivojnovic, Pees, et al.
- 1996
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33
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Machine descriptions to build tools for embedded systems
– Ramsey, Davidson
- 1998
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30
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A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools
– Siska
- 1998
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26
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A formal model and specification language for procedure calling conventions
– Bailey, Davidson
- 1995
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20
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A BDD-based frontend for retargetable compilers
– Leupers, Marwedel
- 1995
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20
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PEAS-I: a hardware/software codesign system for ASIP development
– Sato, Alomary, et al.
- 1994
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19
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RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
– Grun, Halambi, et al.
- 1999
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18
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Optimization of machine descriptions for efficient use
– Gyllenhaal, Hwu, et al.
- 1996
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16
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The MIMOLA Language - Version 4.1
– Bashford, Bieker, et al.
- 1994
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13
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A methodology for accurate performance evaluation in architecture exploration
– Hadjiyiannis, Russo, et al.
- 1999
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11
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A Study on Design Support for Computer Architecture Design
– Akaboshi
- 1996
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11
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Generation of software tools from processor descriptions for hardware/software codesign
– Hartoog, Rowson, et al.
- 1997
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10
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Sigh/sim: An environment for retargetable instruction set simulation
– Lohr, Fauth, et al.
- 1993
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10
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V-SAT: A visual specification and analysis tool for system-on-chip exploration
– Khare, Savoiu, et al.
- 1999
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8
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Automatic generation of DSP program development tools
– Fauth, Knoll
- 1993
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7
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HDL-based Modeling of Embedded Processor Behavior for Retargetable Compilation
– Leupers
- 1998
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7
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Language and compiler for optimizing datapath widths of embedded systems
– Inoue, Tomiyama, et al.
- 1998
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5
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The Zephyr Compiler Infrastructure
– Appel, Davidson, et al.
- 1998
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4
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A programming language for processor based embedded systems
– Inoue, Tomiyama, et al.
- 1998
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4
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Superscalar Processor Design with Hardware Description Language AIDL
– Morimoto, Yamazaki, et al.
- 1994
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4
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Advanced processor design using hardware description language aidl
– Morimoto, Saito, et al.
- 1997
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3
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Behavior extraction of MPU from HDL description
– Akaboshi, Yasuura
- 1994
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2
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A Cycle-Accurate Simulator Toolkit for Soft-Core Processors
– Eko, Yasuura
- 1999
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