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Abstract: Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-level parallelism and improve performance. The techniques include reordering to reduce cache misses originally due to Das et al., blocking to reduce load instructions, and prefetching to prevent multiple load-store units from stalling simultaneously. The techniques improve performance from about 40 Mflops (on a... (Update)
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BibTeX entry: (Update)
Sivan Toledo. Improving memory-system performance of sparse matrix-vector multiplication. In Proceedings of the 8th SIAM Conference on Parallel Processing for Scientific Computing, March 1997. http://citeseer.ist.psu.edu/toledo97improving.html More
@article{ toledo97improving,
author = "S. Toledo",
title = "Improving the memory-system performance of sparse-matrix vector multiplication",
journal = "IBM Journal of Research and Development",
volume = "41",
number = "6",
pages = "711--725",
year = "1997",
url = "citeseer.ist.psu.edu/toledo97improving.html" }
Citations (may not include all citations):107 Software Methods for Improvement of Cache Performance on Sup.. (context) - Porterfield - 1989
79 The effect of ordering on preconditioned conjugate gradient (context) - Duff, Meurant - 1989
70 The design and implementation of a parallel unstructured Eul.. - Das, Mavriplis et al. - 1994
61 Argonne National Laboratory (context) - Balay, Gropp et al. - 1996
27 Characterizing the behavior of sparse algorithms on caches - Temam, Jalby - 1992 ACM DBLP
19 Improving performance of linear algebra algorithms for dense.. (context) - Agarwal, Gustavson et al. - 1994
11 A high performance algorithm using pre-processing for sparse.. (context) - Agarwal, Gustavson et al. - 1992
10 Renumbering unstructured grids to improve the performance of.. - Burgess, Giles - 1995 ACM
The graph only includes citing articles where the year of publication is known.
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