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  to The Graduate School.

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by Robert Thacker, Ganesh C. Gopalakrishnan, Erik Brunvand, Date Chris, J. Myers, Robert R. Kessler, Ann W. Hart
http://www.async.elen.utah.edu/publications/RAT-MSThesis.ps.gz
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Abstract:

committee and by majority vote has been found to be satisfactory.

Citations

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195 Algebraic decision diagrams and their applications. Formal methods in system design – Bahar, Frohm, et al. - 1997
181 Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications – CHU - 1987
180 Modeling and verification of time dependent systems using Time Petri nets – Berthomieu, Diaz - 1991
165 Timing Assumptions and Verification of Finite-State Concurrent Systems – Dill - 1989
133 Asynchronous Sequential Switching Circuits – Unger - 1969
131 Programming in VLSI: From communicating processes to delay-insensitive circuits – Martin - 1990
114 Spectral transforms for large boolean functions with applications to technology mapping – CLARKE, MCMILLAN, et al. - 1993
111 Asynchronous Design Methodologies: An Overview – Hauck - 1995
85 Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification – Bryant - 1995
75 Techniques for Automatic Verification of Real-time Systems – Alur - 1991
73 Automatic Gate- Level Synthesis of Speed-Independent Circuits – Beerel, Meng - 1992
54 Automatic synthesis of locally-clocked asynchronous state machines – Nowick, Dill - 1991
52 Automatic synthesis of asynchronous circuits from high-level specifications – Meng, Brodersen, et al. - 1989
51 The Post Office experience: Designing a large asynchronous chip – Coates, Davis, et al. - 1993
50 Computer-aided synthesis and verification of gate-level timed circuits – Myers - 1995
48 Synthesis of Delay-Insensitive Modules – Molnar, Fang, et al. - 1985
47 Translating concurrent programs into delay-insensitive circuits – Brunvand, Sproull - 1989
45 Some progress in the symbolic verification of timed automata – Bozga, Maler, et al. - 1997
44 Basic gate implementation of speed-independent circuits – Kondratyev, Kishinevsky, et al. - 1994
43 A generalized state assignment theory for transformations on signal transition graphs – Vanbekbergen, Lin, et al. - 1992
42 Synthesis of 3D asynchronous state machines – Yun, Dill, et al. - 1992
41 Translating Programs into Delay-Insensitive Circuits – Ebergen - 1989
35 General conditions for the decomposition of state holding elements – Burns - 1996
23 Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty – Lewis - 1989
22 Decomposition and technology mapping of speed-independent circuits using Boolean relations – Cortadella, Kishinevsky, et al. - 1997
22 Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs – Lavagno - 1992
20 Automatic synthesis of gate-level timed circuits with choice – Myers, Rokicki, et al. - 1995
20 Representing and Modeling Circuits – Rokicki - 1993
19 Efficient timing analysis algorithms for timed state space exploration – Belluomini, Myers - 1997
18 Synthesis of Self-Timed Control Circuits from Graphs: An Example – Chu - 1986
15 Automatic verificaton of timed circuits – Rokicki, Myers - 1994
14 Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs – Pastor, Cortadella - 1993
13 Modeling timing assumptions with trace theory – Burch - 1989
11 A FIFO ring oscillator performance experiment – Molnar, Jones, et al. - 1997
10 Specification and compilation of timed systems – Zheng - 1998
9 Automatic synthesis of gate-level speed-independent circuits – Beerel, Myers, et al. - 1994
9 Application of multi-terminal binary decision diagrams – Clarke, Fujita, et al. - 1995
2 Asynchronous circuit synthesis; persistency and complete state coding constraints in signal transition graphs – Puri, Gu - 1993
2 Synthesis of asynchronous control circuits from symbolic signal transition graphs – Yakovlev, Petrov, et al. - 1993
1 An optimal approach to implementing self-timed logic circuits from signal transition graphs – Chung, Kleeman - 1993