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Abstract: . In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used for specification. For these, so called single appearance schedules provide program memory-optimal uniprocessor implementations. Here, buffer memory minimized schedules are explored among these using an Evolutionary Algorithm (EA). Whereas for a restricted class of graphs, there exist optimal polynomial algorithms, these are not exact and may provide poor results when applied to arbitrary,... (Update)
Context of citations to this paper: More
...deadlocks, etc. The repair procedure incorporated here bases on a topological sort algorithm and is similar to the one described in [7]. The code model is encoded by a flag, which can be in 3 different states: either all actors are implemented using only subroutine calls or...
...extensive looping [Bhattacharyya et al. 1999] with inline code) would be preferable. The present study extends our previous work [Teich et al. 1998] where a single objective EA was used to minimize data memory requirements for a restricted class of schedules (SAS) and...
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BibTeX entry: (Update)
J. Teich, E. Zitzler, and S. S. Bhattacharyya. Buffer memory optimization in dsp applications --- an evolutionary approach. In Fifth International Conference on Parallel Problem Solving from Nature (PPSN-V), pages 885--894, 1998. http://citeseer.ist.psu.edu/teich98buffer.html More
@inproceedings{ teich98buffer,
author = "J{\"u}rgen Teich and Eckart Zitzler and Shuvra S. Bhattacharyya",
title = "Buffer Memory Optimization in {DSP} applications --- An Evolutionary Approach",
booktitle = "Fifth International Conference on Parallel Problem Solving from Nature ({PPSN}-V)",
publisher = "Springer",
address = "Berlin, Germany",
editor = "Agoston E. Eiben and Thomas B{\"a}ck and Marc Schoenauer and Hans-Paul Schwefel",
pages = "885--894",
year = "1998",
url = "citeseer.ist.psu.edu/teich98buffer.html" }
Citations (may not include all citations):4212 Computers and Intractability: A Guide to the Theory of NP-Co.. (context) - Garey, Johnson - 1979
588 Handbook of Genetic Algorithms (context) - Davis - 1991
277 Ptolemy: A framework for simulating and prototyping heteroge.. - Buck, Ha et al. - 1991
210 Synchronous dataflow (context) - Lee, Messerschmitt - 1987
106 Code generation for embedded processors (context) - Marwedel, Goossens - 1995
74 Software Synthesis from Dataflow Graphs (context) - Bhattacharyya, Murthy et al. - 1996
45 High level software synthesis for signal processing systems (context) - Ritz, Pankert et al. - 1992
45 Genetic operators for sequencing problems (context) - Fox, McMahon - 1991
34 Grape: A CASE tool for digital signal parallel processing (context) - Lauwereins, Engels et al. - 1990
30 Scheduling for optimum data memory compaction in block diagr.. (context) - Ritz, Willems et al. - 1995
23 Optimal register assignment to loops for embedded code gener.. - Kolson, Nicolau et al. - 1996
20 Automatic Storage Optimization (context) - Fabri - 1982
8 Optimized software synthesis for digital signal processing a.. - Teich, Zitzler et al. - 1998
7 Lower bounds on memory requirements for statically scheduled.. (context) - Denk, Parhi - 1996
7 Compiling data flow programs for digital signal processing (context) - Bhattacharyya - 1994
6 Register allocation and code scheduling for load/store archi.. (context) - Hsu - 1987
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