See this document in CiteSeerX!

A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk (1998)  (Make Corrections)  (2 citations)
S. Tasiran, S.P. Khatri, S. Yovine, R.K. Brayton, A. Sangiovanni-Vincentelli
Lecture Notes in Computer Science



  Home/Search   Context   Related

 
View or download:
berkeley.edu/pub/M...mcad98.TKYBS.ps.gz
verimag.imag.fr/~yovine...fmcad98.ps.gz
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  berkeley.edu/~serdar/publ...index (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: . We present a timed automaton-based method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traversal of this state space. Based on the topological structure of the circuit, a partitioning of the network and a corresponding conjunctively decomposed OBDD... (Update)

Cited by:   More
Verification of Asynchronous Circuits - Using Timed Automata   (Correct)
On Timing Analysis of Combinational Circuits - Salah, Bozga, Maler   (Correct)

Active bibliography (related documents):   More   All
0.8:   Symbolic Model-Checking for Real-Time Circuits and.. - Frößl, Gerlach, Kropf (1995)   (Correct)
0.5:   Digital Systems Synthesis from Petri Net Descriptions - Marranghello (1998)   (Correct)
0.3:   On the Language Inclusion Problem for Timed Automata.. - Ouaknine, Worrell (2003)   (Correct)

Similar documents based on text:   More   All
0.1:   On The Complexity Of Minimizing The OBDD Size For.. - Sauerhoff, Wegener (1996)   (Correct)
0.0:   A brief summary of the tool KRONOS - Yovine   (Correct)
0.0:   I/O Automaton Models and Proofs for Shared-Key Communication Systems - Lynch (1999)   (Correct)

Related documents from co-citation:   More   All
2:   Some progress in the symbolic verification of timed automata - Bozga, Maler et al. - 1997
2:   Finite-state analysis of asynchronous circuits with bounded temporal uncertainty (context) - Lewis - 1989
2:   Theoretical Computer Science (context) - Alur, Dill et al. - 1994

BibTeX entry:   (Update)

S. Tasiran, S. P. Khatri, S. Yovine, R.K. Brayton and A. Sangiovanni-Vincentelli, A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk, FMCAD'98, 1998. http://citeseer.ist.psu.edu/tasiran98timed.html   More

@article{ tasiran98timed,
    author = "S. Tasiran and S. P. Khatri and S. Yovine and R. K. Brayton",
    title = "A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk",
    journal = "Lecture Notes in Computer Science",
    volume = "1522",
    pages = "149--??",
    year = "1998",
    url = "citeseer.ist.psu.edu/tasiran98timed.html" }
Citations (may not include all citations):
268   A theory of timed automata - Alur, Dill - 1994
69   What good are digital clocks - Henzinger, Manna et al. - 1992
44   Some Progress in the Symbolic Verification of Timed Automata - Bozga, Maler et al. - 1997
28   Timing Analysis of Asynchronous Circuits Using Timed Automat.. - Maler, Pnueli - 1995
18   A conjunctively decomposed Boolean representation for symbol.. (context) - McMillan - 1996
9   Timed Boolean Functions- A Unified Formalism for Exact Timin.. (context) - Lam, Brayton - 1994
8   Hierarchical Timing Analysis Using Conditional Delays (context) - Yalcin, Hayes
5   Paul Pettersson and Wang Yi (context) - Larsen - 1997
3   Verifying Abstractions of Timed Systems - Ta, Alur et al. - 1996
3   A New Model to Uniformly Represent the Function and Timing o.. (context) - FroBetal, Kropf - 1994
2   Sangiovanni-Vincentelli SIS: A System for Sequential Circuit.. (context) - Sentovich, Singh et al. - 1992
2   Verifying Real-Time Properties of MOS-Transistor Circuits In.. (context) - FroBetal, Kropf - 1995
1   Delay Models and Exact Timing Analysis In Logic Synthesis an.. (context) - McGeer, Saldanha et al. - 1993
1   Delay optimization of digital CMOS VLSI circuits by transist.. (context) - Carlson, Lee - 1995
1   siran MOCHA: Modularity in Model Checking To appear in Intl (context) - Alur, Henzinger et al.
1   Physical Design Modeling and Verification Project (context) - Design, Verification et al.
1   STARI: A Case Study in Compositional and Hierarchical Timing.. - Ta, Brayton - 1997
1   Computing Delay with Coupling Using Timed Automata (context) - Ta, Kukimoto et al. - 1997
1   AFTA: A Delay Model for Functional Timing Analysis Proceedin.. (context) - Chandramouli, Whittemore et al. - 1997

Documents on the same site (http://www-cad.eecs.berkeley.edu/~serdar/publications/index.html):   More
BDD Variable Ordering for Interacting Finite State Machines - Aziz, Tasiran, Brayton (1994)   (Correct)
Language Containment of Non-Deterministic Omega-Automata - Tasiran, Hojati, Brayton (1995)   (Correct)
Computing Delay with Coupling Using Timed Automata - Tasiran, Kukimoto, Brayton (1997)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC