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Abstract: The current manufacturing technology, 0.15 m can integrate hundreds of millions of transistors, and the integration density with increase by Moore's law that is the number of transistors that can be integrated on a single die would grow exponentially with time. This proceeding will require lots of task-level parallelism to satisfy processing capacity requirements, for example, creating a demand for huge (on the order of Gbit/s) interconnection bandwidths within a single chip. (Update)
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BibTeX entry: (Update)
Yi-Ran Sun, "Simulation and Performance Evaluation for Networks on Chips", M.Sc. Thesis, Department of Microelectronics and Information Technology, Royal Institute of Technology, Stockholm, Sweden, Dec., 2001. http://citeseer.ist.psu.edu/sun01simulation.html More
@misc{ sun01simulation,
author = "Y. Sun",
title = "Simulation and Performance Evaluation for Networks on Chips",
text = "Yi-Ran Sun, Simulation and Performance Evaluation for Networks on Chips,
M.Sc. Thesis, Department of Microelectronics and Information Technology,
Royal Institute of Technology, Stockholm, Sweden, Dec., 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/sun01simulation.html" }
Citations (may not include all citations):33 Addressing the System-on-a-Chip Interconnect Woes Through Co.. - Sgroi, Sheets et al. - 2001
29 Route Packets, Not Wires: On-Chip Interconnection Networks - Dally, Towles - 2001
28 OSI Reference Model - The ISO Model of Architecture for Open.. (context) - Zimmermann - 1980
27 Surviving the SOC revolution: a guide to platform-based desi.. (context) - Chang, Cooke et al. - 1999
17 System Level Design: Orthogonolization of Concerns and Platf.. (context) - Keutzer, Malik et al. - 2000
6 chip Communication Architecture for OC-768 Network Processor.. (context) - Karim, Nguyen et al. - 2001
6 Blocking in a system on a chip (context) - Hunt - 1996
5 Multithreaded Processor Design (context) - Moore - 1996
5 Implementation of Instruction-level and Thread-level Paralle.. (context) - Forsell - 1997
3 Core design and system-on-a-chip integration (context) - Rincon, Cherichette et al. - 1997
3 System-on-a-Chip: design and test (context) - Rajsuman - 2000
2 Memory module structures for shared memory simulation - Forsell, Leppanen - 2000
2 MTAC--A Multithreaded VLIW Architecture for PRAM Simulation - Forsell - 1997
1 Overview document (context) - Alliance - 1998
1 Studies on the realization of PRAM (context) - Leppanen - 1996
1 The ns Manual (formerly ns Notes and Documentation (context) - Project, between et al. - 2001
http://www.isi.edu/nsnam/ns/tutorial/index.html
http://www.ele.kth.se/NOC/
http://www.isi.edu/nsnam/ns/ns-lists.html
http://www.cs.uwa.edu.au/cnet/
http://www.isi.edu/nsnam/ns/
http://www.isi.edu/nsnam/ns/ns-documentation.html
http://nile.wpi.edu/NS/
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Generic VHDL Implementation of a PCNN with Loadable Coefficients .. - Millberg (1999) (Correct)
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