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Symbolic Methods Applied to Formal Verification and Synthesis in Embedded Systems Design (2000)  (Make Corrections)  (2 citations)
Karsten Strehl



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Abstract: In many of today's technical appliances, embedded systems are deployed on an increasing scale. This trend is expected to massively gain in importance, especially for applications in consumer and automotive electronics, telecommunications, medical engineering, and avionics. Embedded systems can be characterized as follows: . They mostly consist of both hardware and software and perform control or communication tasks within an overall system, to which they are connected via networks, sensors,... (Update)

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...exist and are employed in diverse application domains. An example is a recently introduced model of computation called FunState [5] 6] [7] which combines dataflow properties with finite state machine behavior and is especially suited to embedded systems design. Many other...

...and infinite state dataflow queues. Even the timed FunState model can be verified by combining process networks and timed automata [37]. The verification procedure for FunState models has been implemented, and its e#ciency in comparison to other state set...

Cited by:   More
FunState - An Internal Design Representation for Codesign - Strehl, Thiele, Gries.. (2001)   (Correct)
Interval Diagrams for Efficient Symbolic Verification of.. - Strehl, Thiele (2000)   (Correct)

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3:   Scheduling hardware/software systems using symbolic techniques - Strehl, Thiele et al. - 1999
2:   Interval diagrams: Increasing e#ciency of symbolic real-time verification (context) - Strehl - 1999
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BibTeX entry:   (Update)

Karsten Strehl, Symbolic Methods Applied to Formal Verification and Synthesis in Embedded Systems Design, Ph.D. thesis, Swiss Federal Institute of Technology (ETH) Zurich, Shaker Verlag, Aachen, Germany, ISBN 3-8265-7193-2, March 2000. http://citeseer.ist.psu.edu/strehl00symbolic.html   More

@misc{ strehl00symbolic,
  author = "K. Strehl",
  title = "Symbolic Methods Applied to Formal Verification and Synthesis in Embedded
    Systems Design",
  text = "Karsten Strehl, Symbolic Methods Applied to Formal Verification and Synthesis
    in Embedded Systems Design, Ph.D. thesis, Swiss Federal Institute of Technology
    (ETH) Zurich, Shaker Verlag, Aachen, Germany, ISBN 3-8265-7193-2, March
    2000.",
  year = "2000",
  url = "citeseer.ist.psu.edu/strehl00symbolic.html" }
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Documents on the same site (http://www.tik.ee.ethz.ch/~symbolic):   More
Symbolic Model Checking of Process Networks Using Interval.. - Strehl, Thiele (1998)   (Correct)
Scheduling Hardware/Software Systems Using Symbolic.. - Strehl, Thiele.. (1999)   (Correct)
Interval Diagram Techniques for Symbolic Model Checking of Petri.. - Thiele (1999)   (Correct)

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