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Abstract: A new theory and methodology for the practical verification and synthesis of asynchronous systems is developed to aid in the rapid and correct implementation of complex control structures. Specifications are based on a simple process algebra called CCS that is concise and easy to understand and use. A software prototype CAD tool called Analyze was written as part of this dissertation to allow the principles of this work to be tested and applied. Attention to complexity, efficient algorithms,... (Update)
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...2002, June 10 14, 2002, New Orleans, Louisiana, USA. Copyright 2002 ACM 1 58113 461 4 02 0006 . 5.00. machines [18] Burst Mode AFSMs [15][21] and Direct mapped AFSMs [6] 14] However, only a few of these approaches are suitable for EDA. The fundamental requirement is that...
...control circuits thus increasing their performance. 2) Relative timing assumptions were added to the formal verification tool ANALYZE [22]. 3) Pulsed pipeline control simplified the circuit and increased performance. 4) A footed rather than unfooted domino may yield a faster...
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BibTeX entry: (Update)
K.S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD Thesis, The University of Calgary, Calgary, Alberta, Sept. 1994. http://citeseer.ist.psu.edu/stevens94practical.html More
@phdthesis{ stevens94practical,
author = "Kenneth S. Stevens",
title = "Practical Verification and Synthesis of Low Latency Asynchronous Systems",
year = "1994",
url = "citeseer.ist.psu.edu/stevens94practical.html" }
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The graph only includes citing articles where the year of publication is known.
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