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Practical Verification And Synthesis Of Low Latency Asynchronous Systems (1994)  (Make Corrections)  (14 citations)
Kenneth S. Stevens



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Abstract: A new theory and methodology for the practical verification and synthesis of asynchronous systems is developed to aid in the rapid and correct implementation of complex control structures. Specifications are based on a simple process algebra called CCS that is concise and easy to understand and use. A software prototype CAD tool called Analyze was written as part of this dissertation to allow the principles of this work to be tested and applied. Attention to complexity, efficient algorithms,... (Update)

Context of citations to this paper:   More

...2002, June 10 14, 2002, New Orleans, Louisiana, USA. Copyright 2002 ACM 1 58113 461 4 02 0006 . 5.00. machines [18] Burst Mode AFSMs [15][21] and Direct mapped AFSMs [6] 14] However, only a few of these approaches are suitable for EDA. The fundamental requirement is that...

...control circuits thus increasing their performance. 2) Relative timing assumptions were added to the formal verification tool ANALYZE [22]. 3) Pulsed pipeline control simplified the circuit and increased performance. 4) A footed rather than unfooted domino may yield a faster...

Cited by:   More
Formal Verification of Distributed Mutual-Exclusion.. - Meolic, Kapus, Dugonik..   (Correct)
Modelling and Verification of Delay-Insensitive Circuits.. - Kapoor, Josephs (2003)   (Correct)
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI).. - Kenneth Stevens Senior   (Correct)

Active bibliography (related documents):   More   All
1.6:   Automatic Synthesis of Fast, Compact Self-Timed Control - Stevens (1992)   (Correct)
1.4:   Automatic Synthesis of Fast Compact Self-Timed Control.. - Coates, Davis, Stevens (1993)   (Correct)
1.3:   The Post Office Experience: Designing a Large Asynchronous.. - Davis, Stevens, Coates (1993)   (Correct)

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6:   Computer-Aided Synthesis and Verification of GateLevel Timed Circuits - Myers - 1995
5:   Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications (context) - Chu - 1987
5:   Automatic synthesis of extended burst-mode circuits using generalized C-elements - Yun - 1996

BibTeX entry:   (Update)

K.S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD Thesis, The University of Calgary, Calgary, Alberta, Sept. 1994. http://citeseer.ist.psu.edu/stevens94practical.html   More

@phdthesis{ stevens94practical,
    author = "Kenneth S. Stevens",
    title = "Practical Verification and Synthesis of Low Latency Asynchronous Systems",
    year = "1994",
    url = "citeseer.ist.psu.edu/stevens94practical.html" }
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