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Hardware Support for Thread-Level Speculation (2003)  (Make Corrections)  
J. Gregory Steffan



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Abstract: Novel architectures that support multithreading, for example chip multiprocessors, have become increasingly commonplace over the past decade: examples include the Sun MAJC, IBM Power4, Alpha 21464, and Intel Xeon, HP PA8800. However, only workloads composed of independent threads can take advantage of these processors---to improve the performance of a single application, that application must be transformed into a parallel version. Unfortunately the process of parallelization is extremely... (Update)

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BibTeX entry:   (Update)

@misc{ steffan-hardware,
  author = "J. Gregory Steffan",
  title = "Hardware Support for Thread-Level Speculation",
  url = "citeseer.ist.psu.edu/steffan03hardware.html" }
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Documents on the same site (http://www.eecg.toronto.edu/~steffan/publications.html):   More
Extending Cache Coherence to Support Thread-Level Data.. - Steffan, Colohan, Mowry (1998)   (Correct)
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Improving Value Communication for Thread-Level Speculation - Steffan, Colohan, Zhai.. (2002)   (Correct)

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