J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry  Home/Search
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Abstract: While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performancepotential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads... (Update)
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BibTeX entry: (Update)
J. G. Steffan, C. B. Colohan, A. Zhai, and T. C. Mowry. "A Scalable Approach to Thread-Level Speculation." Intl. Symp. on Computer Architecture, June 2000. http://citeseer.ist.psu.edu/steffan00scalable.html More
@inproceedings{ steffan00scalable,
author = "J. Greggory Steffan and Christopher B. Colohan and Antonia Zhai and Todd C. Mowry",
title = "A scalable approach to thread-level speculation",
booktitle = "{ISCA}",
pages = "1-24",
year = "2000",
url = "citeseer.ist.psu.edu/steffan00scalable.html" }
Citations (may not include all citations):866 Techniques and Tools (context) - Aho, Sethi et al. - 1986
406 TreadMarks: Distributed Shared Memory on Standard Workstatio.. - Keleher, Cox et al. - 1994 DBLP
269 Multiscalar Processors - Sohi, Breach et al. - 1995 ACM DBLP
251 Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers et al. - 1995 DBLP
222 The SGI Origin: A ccNUMA Highly Scalable Server (context) - Laudon, Lenoski - 1997 DBLP
136 superscalar microprocessor (context) - Yeager - 1996
97 The Case for a Single-Chip Multiprocessor (context) - Olukotun, Nayfeh et al. - 1996 ACM DBLP
77 The Potential for Using ThreadLevel Data Speculation to Faci.. - Steffan, Mowry - 1998
74 Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998 ACM DBLP
72 A Dynamic Multithreading Processor - Akkary, Driscoll - 1998 ACM DBLP
72 Data Speculation Support for a Chip Multiprocessor (context) - Hammond, Willey et al. - 1998 ACM DBLP
67 ARB: A Hardware Mechanism for Dynamic Reordering of Memory R.. - Franklin, Sohi - 1996 DBLP
53 Software DSM Protocols that Adapt between Single Writer and .. - Amza, Dwarkadas et al. - 1997 ACM DBLP
38 Architectural Support for Scalable Speculative Parallelizati.. - Cintra, Martnez et al. - 2000
36 Techniques for reducing consistency-relatedinformation in di.. (context) - Carter, Bennett et al. - 1995
30 Clustered Speculative Multithreaded Processors - Marcuello, Gonzlez - 1999 ACM DBLP
26 An Architecture for Mostly Functional Languages (context) - Knight - 1986 ACM DBLP
20 MAJC: Microprocessor Architecture for Java Computing (context) - Tremblay - 1999
19 Architectural Support for Thread-Level Data Speculation - Steffan, Colohan et al. - 1997
12 Hardware for Speculative Parallelization of Partially-Parall.. - Zhang, Rauchwerger et al. - 1999 ACM DBLP
12 Power4: A Dual-CPU Processor Chip (context) - Kahle - 1999
10 Special Issue on Multithreaded Architectures (context) - Tsai, Huang et al. - 1999
6 The Need for Fast Communication in Hardware-Based Speculativ.. - Krishnan, Torrellas - 1999 ACM DBLP
3 Techniques for Speculative Run-Time Parallelization of Loops (context) - Gupta, Nim - 1998 ACM
The graph only includes citing articles where the year of publication is known.
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