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Abstract: This paper presents a practical methodology for the application of formal verification to the industrial design environment "Protocol Compiler". Our verification flow is to first create a testbench and simulate the design. Then we modify the testbench and perform a formal verification technique called assertion checking. The examples are taken from the networking arena. The first is a simplified RS232 transceiver, the second a pipelined FIFO-like buffer written in Verilog. We show that... (Update)
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BibTeX entry: (Update)
@misc{ stangier-applying,
author = "C. Stangier and U. Holtmann",
title = "Applying Formal Verification with Protocol Compiler",
url = "citeseer.ist.psu.edu/stangier01applying.html" }
Citations (may not include all citations):102 Symbolic model checking: 10 20 states and beyond (context) - Burch, Clarke et al. - 1990
96 Expressing interesting properties of programs in proposition.. (context) - Wolper - 1986
19 A System for Compiling and Debugging Structured Data Process.. (context) - Seawright, Holtmann et al. - 1996
12 Clairvoyant: A Synthesis System For Production-Based Specifi.. (context) - Seawright, Brewer - 1994
4 Controller Optimization for Protocol Intensive Applications (context) - Crews, Brewer - 1996
3 Design and Synthesis of Array Structured Telecommunication P.. (context) - Meyer, Seawright et al. - 1997
2 Design of a SPDIF Receiver using Protocol Compiler (context) - Holtmann, Blinzer - 1998
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