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Multiscalar Processors (1995)  (Make Corrections)  (269 citations)
Gurindar Sohi
25 Years ISCA: Retrospectives and Reprints



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Abstract: Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distributed to a number of parallel processing units which reside within a processor complex. Each of these units fetches and executes instructions belonging to its assigned task. The appearance of a single... (Update)

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Dataflow: A Complement to Superscalar - Budiu, Artigas, Goldstein (2005)   (Correct)
Hybrid Transactional Memory - Sanjeev Kumar Michael   (Correct)

Active bibliography (related documents):   More   All
0.1:   Register Communication Strategies for the Multiscalar.. - Vijaykumar Scott (1996)   (Correct)
0.1:   Compiling for the Multiscalar Architecture - Vijaykumar (1998)   (Correct)
0.1:   A Dynamic Approach to Improve the Accuracy of Data Speculation - Andreas Moshovos (1996)   (Correct)

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0.6:   Data Memory Alternatives for Multiscalar Processors - Scott Breach Vijaykumar (1997)   (Correct)
0.3:   Design And Evaluation Of A Multiscalar Processor - Breach (1998)   (Correct)
0.3:   The Anatomy of the Register File in a Multiscalar Processor - Scott Breach Vijaykumar (1994)   (Correct)

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32:   Simultaneous multithreading: Maximizing on-chip parallelism - Tullsen, Eggers et al. - 1995
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27:   Limits of control flow on parallelism - Lam, Wilson - 1992

BibTeX entry:   (Update)

Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414--425, June 22--24, 1995. http://citeseer.ist.psu.edu/sohi95multiscalar.html   More

@inproceedings{ sohi98multiscalar,
    author = "Gurindar S. Sohi and Scott E. Breach and T. N. Vijaykumar",
    title = "Multiscalar Processors",
    booktitle = "25 Years {ISCA}: Retrospectives and Reprints",
    pages = "521-532",
    year = "1998",
    url = "citeseer.ist.psu.edu/sohi95multiscalar.html" }
Citations (may not include all citations):
158   Effective Compiler Support for Predicated Execution Using th.. - Mahlke, Liu et al. - 1992  ACM   DBLP
146   A Comparison of Dynamic Branch Predictors that Use Two Level.. - Yeh, Patt - 1993  ACM   DBLP
112   Highly Concurrent Scalar Processing (context) - Hsu, Davidson - 1986  ACM   DBLP
70   The Expandable Split Window Paradigm for Exploiting Fine-Gra.. - Franklin, Sohi - 1992  ACM   DBLP
47   Detection and Parallel Execution of Independent Instructions (context) - Tjaden, Flynn - 1970
39   The Multiscalar Architecture - Franklin - 1993  ACM
37   Look-Ahead Processors (context) - Keller - 1975  ACM   DBLP
35   The Impact of Synchronization and Granularity on Parallel Sy.. - Chen, Su et al. - 1990
33   Superblock Formation Using Static Program Analysis - Hank, Mahlke et al. - 1993  ACM   DBLP
28   The Anatomy of the Register File in a Multiscalar Processor - Breach, Vijaykumar et al. - 1994
27   Guarded Execution and Branch Prediction in Dynamic ILP Proce.. (context) - Pnevmatikatos, Sohi - 1994  ACM
23   ARB: A Hardware Mechanism for Dynamic Memory Disambiguation (context) - Franklin, Sohi



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Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers, Levy (1995)   (Correct)

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