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Abstract: this paper, we overview the TORCH architecture, describe the TORCH hardware to support boosting, and present the results of a simple static scheduler which performed limited instruction boosting and no load/store reorganization. The simple scheduler and our evaluation system allow us to quickly assess the viability of 1 (Update)
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BibTeX entry: (Update)
Michael D. Smith, Monica S. Lam, and Mark A. Horowitz. Boosting Beyond Static Scheduling in a Superscalar Processor. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 344--354, Seattle, Washington, May 28--31, 1990. http://citeseer.ist.psu.edu/smith90boosting.html More
@inproceedings{ smith90boosting,
author = "M. D. Smith and M. Lam and M. A. Horowitz",
title = "Boosting beyond static scheduling in a superscalar processor",
booktitle = "Proceedings of the 17th Annual Symposium on Computer Architecture",
pages = "344--354",
year = "1990",
url = "citeseer.ist.psu.edu/smith90boosting.html" }
Citations (may not include all citations):407 Trace Scheduling: A Technique for Global Microcode Compactio.. (context) - Fisher - 1981 DBLP
353 Software Pipelining: An Effective Scheduling Technique for V.. (context) - Lam - 1988 ACM DBLP
185 Branch Prediction Strategies and Branch Target Buffer Design (context) - Lee, Smith - 1984 ACM DBLP
130 A VLIW Architecture for a Trace Scheduling Compiler (context) - Colwell - 1988 ACM DBLP
84 Reducing the Cost of Branches (context) - McFarling, Hennessy - 1986 ACM DBLP
82 Limits on Multiple Instruction Issue - Smith, Johnson et al. - 1989 ACM DBLP
67 An Approach to Scientific Array Processing: The Architectura.. (context) - Charlesworth - 1981
61 Some Experiments in Local Microcode Compaction for Horizonta.. (context) - Davidson, Landskov et al. - 1981 DBLP
57 Implementation of Precise Interrupts in Pipelined Processors - Smith, Pleszkun - 1985 ACM DBLP
37 Look-Ahead Processors (context) - Keller - 1975 ACM DBLP
37 The Cydra 5 Departmental Supercomputer (context) - Rau, Yen et al. - 1989 ACM
30 Dynamic Instruction Scheduling and the Astronautics ZS-1 (context) - Smith - 1989 ACM DBLP
14 Architecture and Compiler Tradeoffs for a Long Instruction W.. (context) - Cohn, Gross et al. - 1989 DBLP
10 MIPS Language Programmer's Guide (context) - Systems - 1986
8 Super-Scalar Processor Design - Johnson - 1989
6 SIMP (Single Instruction stream / Multiple instruction Pipel.. (context) - Murakami, Irie et al. - 1989
5 Intel's Secret Is Out (context) - Perry - 1989 ACM
4 An Efficient Hardware Algorithm for Exploiting Multiple Arit.. (context) - Tomasulo
3 Planning a Computer System: Project Stretch (context) - Buchholz - 1962
3 An IBM Second Generation RISC Processor Architecture (context) - Groves, Oehler - 1989
2 The Series 10000 Personal Supercomputer (context) - Inc, Brochure - 1988
1 Microprocessor Report (context) - SPARC, Architecture - 1988
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