Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven, Kees Vissers  Home/Search
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Abstract: This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMediaCPU64 architecture, which consists of a Reconfigurable Functional Unit and its associated instructions. Then, we address the decoding of variable-length codes on such extended TriMedia and describe the architecture and FPGAimplementation of a Variable-Length Decoder (VLD)... (Update)
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BibTeX entry: (Update)
M. Sima, S. Cotofana, S. Vassiliadis, J. T. van Eijndhoven, and K. Vissers. MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia Processor. In IEEE International Conference on Computer Design (ICCD2001. http://citeseer.ist.psu.edu/sima01mpeg.html More
@misc{ sima-mpeg,
author = "M. Sima and S. Cotofana and S. Vassiliadis and J. van Eijndhoven and K.
Vissers",
title = "MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia
Processor",
text = "M. Sima, S. Cotofana, S. Vassiliadis, J. T. van Eijndhoven, and K. Vissers.
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia
Processor. In IEEE International Conference on Computer Design (ICCD2001.",
url = "citeseer.ist.psu.edu/sima01mpeg.html" }
Citations (may not include all citations):176 Garp: A MIPS Processor with a Reconfigurable Coprocessor - Hauser - 1997
109 A High Performance Microarchitecture with Hardware-Programma.. - Razdan - 1994
109 MPEG Video Compression Standard (context) - Mitchell, Pennebaker et al. - 1996
58 A Time-Multiplexed FPGA (context) - Trimberger, Carberry et al. - 1997
23 ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accele.. (context) - Kastrup, Bink et al. - 1999
15 TriMedia CPU64 Architecture (context) - van Eijndhoven, Sijstermans et al. - 1999
14 Architecture of FPGAs and CPLDs: A Tutorial - Brown - 1996
10 A Taxonomy of Custom Computing Machines - Sima, Vassiliadis et al. - 2000
7 TriMedia CPU64 Application Development Environment (context) - Pol, Aarts et al. - 1999
5 ACEX 1K Programmable Logic Family (context) - Corporation - 2000
3 8 8 IDCT Implementation on an FPGA-augmented TriMedia (context) - Sima, Cotofana et al. - 2001
3 VLD Performance on TriMedia-CPU64 (context) - Pol - 2000
3 Dynamically Programmable Gate Array with Multiple Context (context) - DeHon, Jr et al. - 1998
The graph only includes citing articles where the year of publication is known.
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Microcoded Reconfigurable Embedded Processors: Current.. - Wong, Vassiliadis.. (2001) (Correct)
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