(Enter summary)
Abstract: Media- and telecommunications-focused processors,
increasingly designed as deeply pipelined, staticallyscheduled
VLIWs, rely on loop buffers for low-overhead execution
of simple loops. Key loops containing control flow
pose a substantial problem---full predication has a high encoding
overhead, and partial predication techniques do not
support if-conversion, the transformation of general acyclic
control flow into predicated blocks. Using a set of significant
media processing benchmarks, drawn... (Update)
Context of citations to this paper: More
.... ZOL can be partitioned into two sets, depending on whether this optimization is performed before or after the code generation process (e.g. [18, 19]) Usually, it is much easier to recognize loops before performing code generation since the program code is more structured....
...last writer which potentially depends on some qualifying predicate, adding complexity and propagation delay. This issue was mentioned in [21], and alluded to in [19] In this paper we examine a light weight form of select predication, called Phi Predication, where only a small...
Cited by: More
Phi-Predication for Light-Weight If-Conversion - Chuang, Calder, Ferrante (2003)
(Correct)
Energy aware Compilation for DSPs with SIMD instructions - Lorenz, Wehmeyer, Dräger (2002)
(Correct)
Active bibliography (related documents): More All
0.5: Modulo Schedule Buffers - Merten, Hwu (2001)
(Correct)
0.5: The Impact SC140 Code Generator - Shannon (2002)
(Correct)
0.3: Custom-Instruction Synthesis for Extensible-Processor.. - Sun, Ravi, Raghunathan.. (2004)
(Correct)
Similar documents based on text: More All
0.7: Accurate and Efficient Predicate Analysis with Binary Decision.. - Sias, al. (2000)
(Correct)
0.5: The Program Decision Logic Approach to Predicated.. - August, Sias, Puiatti, .. (1999)
(Correct)
0.5: A Comparison of Full and Partial Predicated Execution Support for .. - Mahlke (1995)
(Correct)
BibTeX entry: (Update)
J. Sias, H. Hunter, and W. Hwu. Enhancing loop buffering of media and telecommunications applications using low-overhead predications. In Proceedings of the 34th Annual International Symposium on Microarchitecture, December 2001. http://citeseer.ist.psu.edu/sias01enhancing.html More
@misc{ sias01enhancing,
author = "J. Sias and H. Hunter and W. Hwu",
title = "Enhancing loop buffering of media and telecommunications applications using
low-overhead predications",
text = "J. Sias, H. Hunter, and W. Hwu. Enhancing loop buffering of media and telecommunications
applications using low-overhead predications. In Proceedings of the 34th
Annual International Symposium on Microarchitecture, December 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/sias01enhancing.html" }
Citations (may not include all citations):
353
Software pipelining: an effective scheduling technique for V.. (context) - Lam - 1988
320
MediaBench: A tool for evaluating and synthesizing multimedi..
- Lee, Potkonjak et al. - 1997
158
Effective compiler support for predicated execution using th..
- Mahlke, Lin et al. - 1992
150
Iterative modulo scheduling: An algorithm for software pipel..
- Rau - 1994
52
A compilation technique for software pipelining of loops wit.. (context) - Ebcioglu - 1987
43
Integrated predicated and speculative execution in the IMPAC..
- August, Connors et al. - 1998
43
A comparison of full and partial predicated execution suppor..
- Mahlke, Hank et al. - 1995
42
An integrated cache timing and power model (context) - Reinman, Jouppi - 1999
24
Compiler technology for future microprocessors
- Hwu, Hank et al.
24
Compiling for the Cydra 5 (context) - Dehnert, Towle - 1993
21
On predicated execution
- Park, Schlansker - 1991
20
TMSC CPU and Instruction Set Reference Guide (context) - Incorporated, CPU et al. - 1999
17
Instruction fetch mechanisms for VLIW architectures with com..
- Conte, Banerjia et al. - 1996
11
Clustered instruction-level parallel processors (context) - Faraboschi, Desoli et al. - 1998
9
IA-64 Architecture Software Developer's Manual (context) - Corporation - 2000
7
Modulo scheduling for a fullydistributed clustered VLIW arch.. (context) - Sanchez, Gonzalez - 2000
6
HPL-PD architecture specification: Version 1.1 (context) - Kathail, Schlansker et al. - 2001
4
SC140 DSP Core Reference Manual (context) - Technology - 2000
4
An architecture framework for introducing predication into e..
- Connors, Puiatti et al. - 1999
3
Exploiting data forwarding to reduce the power budget of VLI..
- Sami, Sciuto et al. - 2001
2
Digital cellular communications system; enhanced full rate (.. (context) - TC-SMG - 1997
1
Efficient exploitation of a zero overhead loop buffer (context) - Uh, Wang et al. - 1999
Documents on the same site (http://www.crhc.uiuc.edu/Impact/people/current/sias.html): More
The Program Decision Logic Approach to Predicated.. - August, Sias, Puiatti, .. (1999)
(Correct)
Condition Awareness Support For Predicate Analysis And Optimization - Sias (1999)
(Correct)
Integrated Predicated and Speculative Execution in .. - August, Connors.. (1998)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC