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191
The algebra of connectors – structuring interaction
- in BIP. In EmSoft
, 2007
"... Abstract—We provide an algebraic formalization of connectors in the BIP component framework. A connector relates a set of typed ports. Types are used to describe different modes of synchronization, in particular, rendezvous and broadcast. Connectors on a set of ports P are modeled as terms of the al ..."
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Cited by 61 (12 self)
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Abstract—We provide an algebraic formalization of connectors in the BIP component framework. A connector relates a set of typed ports. Types are used to describe different modes of synchronization, in particular, rendezvous and broadcast. Connectors on a set of ports P are modeled as terms of the algebra ACðPÞ, generated from P by using a binary fusion operator and a unary typing operator. Typing associates with terms (ports or connectors) synchronization types—trigger or synchron—that determine modes of synchronization. Broadcast interactions are initiated by triggers. Rendezvous is a maximal interaction of a connector that includes only synchrons. The semantics of ACðPÞ associates with a connector the set of its interactions. It induces on connectors an equivalence relation which is not a congruence as it is not stable for fusion. We provide a number of properties of ACðPÞ used to symbolically simplify and handle connectors. We provide examples illustrating applications of ACðPÞ, including a general component model encompassing methods for incremental model decomposition and efficient implementation by using symbolic techniques. Index Terms—Real-time and embedded systems, system architectures, integration, and modeling, systems specification methodology, interconnections, architecture. Ç
Towards a higher-order synchronous data-flow language
- In EMSOFT’04
, 2004
"... The paper introduces a higher-order synchronous data-flow language in which communication channels may themselves transport programs. This provides a mean to dynamically reconfigure data-flow processes. The language comes as a natural and strict extension of both Lustre and Lucid Synchrone. This ext ..."
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Cited by 33 (3 self)
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The paper introduces a higher-order synchronous data-flow language in which communication channels may themselves transport programs. This provides a mean to dynamically reconfigure data-flow processes. The language comes as a natural and strict extension of both Lustre and Lucid Synchrone. This extension is conservative, in the sense that a first-order restriction of the language can receive the same semantics. We illustrate the expressivity of the language with some examples, before giving the formal semantics of the underlying calculus. The language is equipped with a polymorphic type system allowing types to be automatically inferred and a clock calculus rejecting programs for which synchronous execution cannot be statically guaranteed. To our knowledge, this is the first higher-order synchronous data-flow language where stream functions are first class citizens. Categories and Subject Descriptors C.3 [Special-purpose and application-based systems]: Real-time and embedded systems; D.3.2 [Language classifications]: Data-flow languages; F.3.2 [Semantics of programming languages]: Operational semantics.
Optimizations For Faster Execution Of Esterel Programs
, 2004
"... The fine-grained parallelism and the need for determinism are traditional issues in the design of real-time embedded software. In addition, the increasing complexity of the specifications requires an increasing use of higher level formalisms. The Esterel language offers natural solutions to all thes ..."
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Cited by 26 (0 self)
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The fine-grained parallelism and the need for determinism are traditional issues in the design of real-time embedded software. In addition, the increasing complexity of the specifications requires an increasing use of higher level formalisms. The Esterel language offers natural solutions to all these problems, but its compilation proved challenging, so that efficient compilation techniques have only recently been proposed. Consisting essentially in direct simulation of the reactive primitives of the language, these techniques now need to be accommodated with traditional issues of Esterel: the definition of formal semantics, the constructive causality, and the design of analysis and optimization methods that are both efficient and correct.
Modular code generation from synchronous block diagrams — modularity vs. code size
- in Proc. POPL
, 2009
"... We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composit ..."
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Cited by 26 (6 self)
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We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the embedded software domain, such as Simulink and SCADE. Code is modular in the sense that it is generated for a given composite block independently from context (i.e., without knowing in which diagrams the block is to be used) and using minimal information about the internals of the block. In previous work, we have shown how modular code can be generated by computing a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. We have also introduced a quantified notion of modularity in terms of the number of interface functions generated per block, and showed how to minimize this number, which is essential for scalability. Finally, we have exposed
Implementing Synchronous Models on Loosely Time Triggered Architectures
- IEEE Transactions on Computers
"... Synchronous systems offer a clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models and then implementing the specifications in a less restrictive platform allow to address a much larger design space. Th ..."
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Cited by 24 (9 self)
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Synchronous systems offer a clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models and then implementing the specifications in a less restrictive platform allow to address a much larger design space. The key issue in this approach is maintaining semantic equivalence between the synchronous model and its implementation. We address this problem by showing how to map a synchronous model onto a loosely timetriggered architecture that is fairly straightforward to implement as it does not require global synchronization or blocking communication. We show how to maintain semantic equivalence between specification and implementation using an intermediate model (similar to a Kahn process network but with finite queues) that helps in defining the transformation. Performance of the semantic preserving implementation is studied for the general case as well as for a few special cases. 1
Period Optimization for Hard Real-time Distributed Automotive Systems
- in Proceedings of the 44th IEEE/ACM Design Automation Conference
, 2007
"... The complexity and physical distribution of modern active-safety automotive applications requires the use of distributed architec-tures. These architectures consist of multiple electronic control units (ECUs) connected with standardized buses. The most com-mon configuration features periodic activat ..."
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Cited by 22 (5 self)
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The complexity and physical distribution of modern active-safety automotive applications requires the use of distributed architec-tures. These architectures consist of multiple electronic control units (ECUs) connected with standardized buses. The most com-mon configuration features periodic activation of tasks and mes-sages coupled with run-time priority-based scheduling. The correct deployment of applications on such architectures requires end-to-end latency deadlines to be met. This is challenging since dead-lines must be enforced across a set of ECUs and buses, each of which supports multiple functionality. The need for accommodat-ing legacy tasks and messages further complicates the scenario. In this work, we automatically assign task and message periods for distributed automotive systems. This is accomplished by lever-aging schedulability analysis within a convex optimization frame-work to simultaneously assign periods and satisfy end-to-end la-tency constraints. Our approach is applied to an industrial case study as well as an example taken from the literature and is shown to be both effective and efficient.
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams
- In Design, Automation, and Test in Europe (DATE’08). ACM
, 2008
"... We present several methods to generate modular code from synchronous hierarchical block diagrams. Modularity means code is generated for a given macro (i.e., composite) block independently from context, that is, without knowing where this block is to be used, and also with minimal knowledge about it ..."
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Cited by 22 (8 self)
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We present several methods to generate modular code from synchronous hierarchical block diagrams. Modularity means code is generated for a given macro (i.e., composite) block independently from context, that is, without knowing where this block is to be used, and also with minimal knowledge about its sub-blocks. We achieve this by generating a set of interface functions for each block and a set of dependencies between these functions that is exported along with the interface. The main trade-off is the degree of modularity (number of interface functions) vs. reusability (the set of diagrams that the block can be used in without creating dependency cycles). 1
Compositional modeling and refinement for hierarchical hybrid systems
- Journal of Logic and Algebraic Programming
, 2006
"... In this paper, we develop a theory of modular design and refinement of hierarchical hybrid systems. In particular, we present compositional trace-based semantics for the language Charon that allows modular specification of interacting hybrid systems. For hierarchical description of the system archit ..."
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Cited by 17 (2 self)
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In this paper, we develop a theory of modular design and refinement of hierarchical hybrid systems. In particular, we present compositional trace-based semantics for the language Charon that allows modular specification of interacting hybrid systems. For hierarchical description of the system architecture, Charon supports building complex agents via the operations of instantiation, hiding, and parallel composition. For hierarchical description of the behavior of atomic components, Charon supports building complex modes via the operations of instantiation, scoping, and encapsulation. We develop an observational trace semantics for agents as well as for modes, and define a notion of refinement for both, based on trace inclusion. We show this semantics to be compositional with respect to the constructs in the language. 1
Performance debugging of Esterel specifications
- In International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS
, 2008
"... Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, where the computation/communication associated with the processing of all even ..."
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Cited by 16 (3 self)
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Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, where the computation/communication associated with the processing of all events occurring within the same “clock tick ” are assumed to happen instantaneously (or in zero time). In reality, Esterel specifications get compiled to implementations (such as C code) which do not satisfy the perfect synchrony assumption. Hence, platform-specific timing analysis of such implementations is an important research topic. Interest in this area has lately been renewed with the recent advances in Worst-case Execution Time (WCET) analysis techniques. In this paper we perform WCET analysis on sequential C code and exploit the structure of the code generated from Esterel specifications to obtain tight WCET estimates. Such estimates can validate Esterel-level assumptions on the instantaneous processing of signals or events that occur together. More importantly, they can be used to identify parts of the specification which might pose as timing/performance bottlenecks with respect to the underlying platform. This is done by exploiting traceability links between Esterel specifications and the generated C code, which map the time-critical computations at the C-level back to the Esterel-level. This not only allows a designer to optimize or simplify Esterel specifications, but also choose/configure suitable implementation platforms. We show the results of our WCET analysis on a set of standard Esterel benchmarks and illustrate the utility of our model-code traceability technique using an Esterel specification of a reflex game application.
