For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

Abstract not found

Applying the Design of Experiments methodology to the evaluation of BDD variable ordering algorithms has yielded a number of conclusive results. The methodology relies on the recently introduced equivalence classes of functionally perturbed circuits that maintain logic invariance, or are within f1, 2, ...g-minterms of the original reference circuit function, also maintaining entropy-invariance. For some of the current variable ordering algorithms and tools, the negative results include: (1) statistically significant sensitivity to naming of variables, (2) confirmation that a number of variable ordering algorithms are statistically equivalent to a random variable order assignment, and (3) observation of a statistically anomalous variable ordering behavior of a wellknown benchmark circuit isomorphic class when analyzed under a single and multiple outputs. On the positive side, the methodology supports a statistically significant merit evaluation of any newly introduced variable ordering ...

The development of next-generation CAD tools and FPGA architectures require benchmark circuits to experiment with new algorithms and architectures. There has always been a shortage of good public benchmarks for these purposes, and even companies that have access to proprietary customer designs could benefit from designs that meet size and other particular specifications. In this paper, we present a new method of generating realistic synthetic benchmark circuits to help alleviate this shortage. The method significantly improves the quality of previous work by imposing a hierarchy of circuits through clustering and by using a simpler method of characterizing the nature of sequential circuits. Also, in contrast to current constructive generation methods [7-9,11-16,18,19], we employ new iterative techniques in the generation that provide better control over the generated circuit’s characteristics. As in previous work, we assess the realism of the generated circuits by comparing properties of real circuits and generated "clones " of the real circuit after placement and routing. On average, the real and clone circuits ' total detailed wirelength differ by only 14%, a major improvement over previous results. In addition, the minimum track count is within 14 % and the critical path delay is within 10%.

The bigraph crossing problem, embedding the two vertex sets of a bipartite graph G = (V0;V1;E) along two parallel lines so that edge crossings are minimized, has application to circuit layout and graph drawing. We consider the case where both V0 and V1 can be permuted arbitrarily -- both this and the case where the order of one vertex set is fixed are NP-hard. Two new heuristics that perform well on sparse graphs such as occur in circuit layout problems are presented. The new heuristics outperform existing heuristics on graph classes that range from application-specific to random. Our experimental design methodology ensures that differences in performance are statistically significant and not the result of minor variations in graph structure or input order.

Traditional approaches to the measurement of performance for CAD algorithms involve the use of sets of so-called “benchmark circuits.” In this paper, we demonstrate that current procedures do not produce results which accuratelycharacterize the behavior of the algorithms under study. Indeed, we show that the apparent advances in algorithms which are documented by traditional benchmarking maywell be due to chance, and not due to anynew properties of the algorithms. As an alternative, we introduce a new methodologyfor the characterization of CAD heuristics which employs wellstudied design of experiments methods. We show through numerous examples how such methods can be applied to evaluate the behavior of heuristics used in BDD variable ordering.

This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of FPGA partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100K CLBs (500K equivalent gates), for instance, takes only two minutes on a standard UNIX workstation. The analysis of a large number of netlists from real designs lead us to identify the following five different kinds of sub-blocks: Regular combi-national logic, irregular combinational logic, combinational and sequential logic, memory blocks, and interconnections. Therefore, our generator integrates a sub-generator for each of these types of netlist. The comparison of the partitioning results of industrial netlists with those obtained from generated netlists of the same size shows that the generated netlists behave similarly to the originals in terms of average filling rate and average pin utilization. 1.

. Despite more than a decade of experience with the use of standardized benchmark circuits, meaningful comparisons of EDA algorithms remain elusive. In this paper, we introduce a new methodology for characterizing the performance of Binary Decision Diagram (BDD) algorithms. Our method involves the synthesis of large equivalence classes of functionally perturbed circuits, based on a known reference circuit. We demonstrate that such classes induce controllable distributions of BDD algorithm performance, which provide the foundation for statistically significant comparison of different algorithms. 1 Introduction We introduce methods rooted in the Design of Experiments, first formalized in [1], to evaluate the properties of programs which implement Reduced, Ordered Binary Decision Diagrams [2] (hereafter referred to as BDDs). The choice of BDD variable order has a profound impact on the size of the BDD data structure. Determining an optimal variable ordering is an NP-hard problem upon whi...

In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.

This paper introduces the background and motivation for the two special sessions at ISCAS'99. The sessions bring together eight papers, each rooted in the methodology of experimental design, and contributed by collaborating teams of distributed participants. The paper briefly outlines the premises of the companion papers that follow, provides a brief description of a typical experimental design, and introduces a design for archival of data sets and results that are to be readily accessible on the Web. Keywords: design of experiments, circuit equivalence classes, benchmarking. 1 Introduction More than a thousand mathematical problems arising in engineering and science have been shown to be NP-hard. Data sets such as ISCAS'85, ISCAS'89, and extensions introduced at logic and layout synthesis workshops, e.g. [1, 2, 3], are representative of such problems. They have captured a large following of researchers in CAD that `benchmark' their algorithms on various subsets of these data sets --...