Bit-vector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended theory which includes arithmetic. Although deciding equality in such a theory is NP-hard, our implementation is efficient for many practical examples. We believe this to be the first such implementation which is efficient, automatic, and complete.

Formal verification has become one of the most important steps in circuit design. In this context the verification of high-level Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on Word-Level Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn out to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach. 1 Introduction Nowadays modern circuit design can contain several million transistors. For this, also verification of such large designs becomes more and more difficult, since pure simu...

Word-Level Decision Diagrams (WLDDs), like EVBDDs, *BMDs, HDDs, K*BMDs, are powerful tools in circuit verification. Especially for some arithmetic circuits, like multipliers, for the first time formal verification was possible using WLDDs. Beside a good variable ordering and the decomposition types the size of a WLDD essentially depends on the grouping of the outputs. In this paper we study output grouping in more detail. We give examples showing that an exponential reduction or an exponential blow-up can be obtained dependent on grouping. We describe efficient heuristics for output grouping given a circuit description in the form of a netlist. Experimental results are given to demonstrate the efficiency of our approach. 1

Bit-level and word-level based Decision Diagrams (DDs) have led to significant advances in the area of Computer Aided Design (CAD). Recently, a new data structure for the word-level, called Kronecker Multiplicative BMDs (K*BMDs), has been presented. We study manipulation algorithms for K*BMDs: Using K*BMDs it is possible to represent functions efficiently, that have a good word-level description (like multipliers). On the the other hand K*BMDs are also applicable to verification problems at the bit-level. We clarify the relation between bit- and word-level representation which is of importance in particular in the context of verification. Experiments show that *BMDs are not wellsuited for the bit-level. On the other hand OBDDs are not applicable on the word-level. We present algorithms that allow to dynamically switch between bit-level and word-level. We discuss a method for changing the decomposition type and variable order. First experiments demonstrate the efficiency...

Multiplicative Binary Moment Diagrams (*BMDs) have recently been introduced as a data structure for verification. Using *BMDs it was for the first time possible to verify multiplier circuits with up to 256 bits. In this paper we use a modification of *BMDs, called positive *BMDs (p*BMDs), that allows to apply dynamic variable ordering, that is the most promising minimization technique for decision diagrams, to *BMDs. Furthermore, we study *BMDs representing Boolean functions. We show that in this case for some operations polynomial algorithms can be given, while the general case of integer-valued functions requires exponential effort. Experimental results demonstrate that p*BMDs clearly outperform *BMDs with respect to runtime during dynamic minimization, while keeping (nearly) all advantages. I. Introduction Most formal approaches in verification nowadays make use of function representation by Decision Diagrams (DDs). In this context Ordered Binary Decision Diagrams (OBDDs) [4] hav...

Word-Level Decision Diagrams (WLDDs), like BMDs or KBMDs, have been introduced to overcome the limitations of Binary Decision Diagrams (BDDs), which are the state-of-the-art data structure to represent and manipulate Boolean functions. However, the size of these graph types largely depends on the variable ordering, i.e. it may vary from linear to exponential. In the meantime, dynamic approaches to find a good variable ordering are also known for WLDDs. In this paper we show how these approaches can be accelerated significantly using a combination of a lower bound computation and synthesis operations. In the experiments it turned out that by this technique, the runtime for dynamic minimization can be reduced by more than 40% on average without loss of quality. 1 Introduction Formal verification has become one of the most important steps in circuit design. Since modern circuit designs can contain several million transistors, also verification of such large designs becomes more and m...