Results 1 - 10
of
10
Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip
- IEEE Symposium on Field-Programmable Custom Computing Machines
, 2004
"... When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performa ..."
Abstract
-
Cited by 9 (2 self)
- Add to MetaCart
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of the SoC. To automate the layout of reconfigurable subsystems for systems-on-a-chip, we present the Circuit Generator Method. The Circuit Generator Method enables a designer to leverage the regularity that exists in FPGAs, creating structures that have only the needed resources to support the specified application domain. To facilitate this we have created generators that automatically produce the various components of the custom reconfigurable device. Compared to the unaltered full-custom tile, we achieve designs that are on average approximately 46 % smaller and 16 % faster, while continuing to support the algorithms in the particular application domain. 1.
Automatic transistor and physical design of FPGA tiles from an architectural specification
- in ACM/SIGDA Int’l Symp. Field-Programmable Gate Arrays
, 2003
"... One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of ..."
Abstract
-
Cited by 9 (3 self)
- Add to MetaCart
(Show Context)
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA. It also generates a cell-level netlist that is placed and routed automatically. The architectural specification is the one used as input to the VPR [3] architectural exploration tool. The output is the mask-level layout of a single tile that can
FPGA Switch Block Layout and Evaluation
- In Proceedings of IEEE/ACM Int. Symp. on Field Programmable Gate Arrays
, 2002
"... This paper presents abstract layout techniques for a variety of FPGA switch block architectures. We evaluate the relative density of sub-set, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also d ..."
Abstract
-
Cited by 8 (0 self)
- Add to MetaCart
(Show Context)
This paper presents abstract layout techniques for a variety of FPGA switch block architectures. We evaluate the relative density of sub-set, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks, and good re-sults for large switch blocks. For switch blocks with general con-nectivity, we develop a representation and a layout evaluation tech-nique. We use these techniques to compare a variety of small switch blocks. We find that the traditional Xilinx-style, subset switch block is superior to the other proposed architectures. Finally, we have hand-designed some small switch blocks to confirm our re-sults.
The SFRA: a corner-turn FPGA architecture
- in Proceedings of the 2004 ACM/SIGDA 12th international
, 2004
"... ABSTRACT FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better to employ fixed-frequency FPGAs operating at a high clock frequency. Such fixed-frequency arrays require pipelin ..."
Abstract
-
Cited by 5 (2 self)
- Add to MetaCart
(Show Context)
ABSTRACT FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better to employ fixed-frequency FPGAs operating at a high clock frequency. Such fixed-frequency arrays require pipelined interconnect structures, which are difficult to support in a traditional FPGA architecture. We have developed a novel approach, called a "corner-turn" interconnect, based on a Manhattan array of logically depopulated Sboxes with full connectivity but limited routability. This interconnect supports new polynomial-time routing techniques while maintaining conventional placement and other upstream toolflow. We have used the corner-turn interconnect to define a fixed-frequency FPGA architecture, the SFRA, that is largely compatible with the Xilinx Virtex while providing higher speed, pipelined operation. Our tools automatically repipeline designs to operate at the SFRA's intrinsic clock frequency. Since the arrays are largely compatible, we directly compare the SFRA with the Virtex on four benchmark designs. On these benchmarks, the SFRA offers higher throughput and competitive throughput per area. The SFRA routing and retiming tools also run one to two orders of magnitude faster than their Xilinx counterparts.
Non-Rectangular Embedded Programmable Logic Cores
, 2002
"... As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, exce ..."
Abstract
-
Cited by 3 (0 self)
- Add to MetaCart
As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. However, most CAD algorithm and programmable logic architecture research targets stand-alone field programmable gate arrays (FPGA's), which are invariably square or rectangular. In this thesis, we enable researchers...
CHANNEL WIDTH REDUCTION TECHNIQUES FOR SYSTEM-ON-CHIP CIRCUITS IN FIELD-PROGRAMMABLE GATE ARRAYS
, 2006
"... Users of field-programmable gate arrays (FPGAs) typically measure the size of a FPGA by its logic capacity. If a design fits within the logic capacity limits of an FPGA, it is generally assumed that it must also be routable. To ensure this high routability, FPGA vendors typically over-design the rou ..."
Abstract
-
Cited by 2 (0 self)
- Add to MetaCart
(Show Context)
Users of field-programmable gate arrays (FPGAs) typically measure the size of a FPGA by its logic capacity. If a design fits within the logic capacity limits of an FPGA, it is generally assumed that it must also be routable. To ensure this high routability, FPGA vendors typically over-design the routing network. Despite this over-design, there may still be circuits that remain un-routable in a given FPGA family. This thesis presents two new computer-aided design (CAD) tools, DHPack and Un/DoPack, that are able to route these un-routable circuits by trading off logic utilization for interconnect. DHPack uses the natural design hierarchy of the circuit to identify high congestion regions. For a set of benchmark circuits used in this thesis, DHPack is able to reduce channel width by 13 % with a small area increase of 3%. DHPack can continue to decrease channel width by 29 % with a larger area increase of 146%. Un/DoPack improves on DHPack by targeting hard channel width constraints without having to rely on the design hierarchy of the circuit to perform congestion estimation. For a set of benchmark circuits presented in this thesis, Un/DoPack can reduce channel width by 38 % with an 18 % penalty in critical path delay and 64% increase in area. The primary application of these tools is to make previously unroutable circuits routable by using an FPGA with more logic.
On optimal irregular switch box designs
- in Field Programmable Logic and Application
, 2004
"... Abstract. In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on different sides. The results drawn from our system of linear Diophantine equations based formulation turn ou ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
(Show Context)
Abstract. In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on different sides. The results drawn from our system of linear Diophantine equations based formulation turn out to be general. We prove that the divideand-conquer (reduction) design methodology can also be applied to the irregular cases. Namely, an optimal arbitrarily large irregular or regular switch box can be obtained by combining small prime switch boxes, which largely reduces the design complexity. We revise the known VPR router for our experiments and show that the design optimality of switch boxes does pay off.
