Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing new processor architectures, as well as when evaluating the performance of new processor enhancements. However, despite this dependence on simulators, statistically rigorous simulation methodologies are not typically used in computer architecture research. A formal methodology can provide a sound basis for drawing conclusions gathered from simulation results by adding statistical rigor, and consequently, can increase confidence in the simulation results. This paper demonstrates the application of a rigorous statistical technique to the setup and analysis phases of the simulation process. Specifically, we apply a Plackett and Burman design to: 1) identify key processor parameters, 2) classify benchmarks based on how they affect the processor, and 3) analyze the effect of processor performance enhancements. Our technique expands on previous work by applying a statistical method to improve the simulation methodology instead of applying a statistical model to estimate the performance of the processor.

Due to cost, time, and flexibility constraints, simulators are needed to explore the design space when developing a new processor architecture as well as when evaluating the performance of new compiler-based and microarchitectural mechanisms. However, improperly choosing the processor parameters, such as the cache size, the associativity, the number of functional units, and so forth, can significantly affect the simulation results, independent of any new mechanism being evaluated. As a first step in developing a methodology to appropriately choose the processor parameters to be used in a simulation, we quantify the effect of a select group of ten key parameters on the total execution time (measured in simulated cycles) using the statistical analysis of variance (ANOVA) technique. Our results show that, for the commonly used SimpleScalar simulator, the number of reorder buffer entries, the L1 D-Cache associativity and size, and the memory latency account for approximately 75 % of the total observed variation in the execution time. Conversely, the branch predictor has surprisingly little effect, only about 1%. In addition, we find that interactions between parameters also have little effect on the total execution time. This work clearly demonstrates that poor choices of simulated processor parameter values, or even a single poor choice, can significantly affect the simulation results and thereby lead to erroneous conclusions about the processor or mechanism being simulated. 1

Abstract — Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of the 3D integration technology. In this paper, we investigate the scalability issues of 3D die-stacked arithmetic units. We explore the behavior of the 3D-integrated arithmetic circuits with increasing issue-width (parallel execution capability), transistor sizing, and temperature. We show that the 3D-integrated units have a lower latency degradation and lower rate of increase in energy consumption than the planar circuits with increasing issue-widths and operating temperatures. We demonstrate that the 3D-integrated circuits have less sensitivity to transistor sizing than the planar circuits. The better scalability of 3D circuits may extend the silicon roadmap for a few more generations. I.

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