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59
The Viterbi algorithm
 Proceedings of the IEEE
, 1973
"... vol. 6, no. 8, pp. 211220, 1951. [7] J. L. Anderson and J. W..Ryon, “Electromagnetic radiation in accelerated systems, ” Phys. Rev., vol. 181, pp. 17651775, 1969. [8] C. V. Heer, “Resonant frequencies of an electromagnetic cavity in an accelerated system of reference, ” Phys. Reu., vol. 134, pp. A ..."
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Cited by 985 (3 self)
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vol. 6, no. 8, pp. 211220, 1951. [7] J. L. Anderson and J. W..Ryon, “Electromagnetic radiation in accelerated systems, ” Phys. Rev., vol. 181, pp. 17651775, 1969. [8] C. V. Heer, “Resonant frequencies of an electromagnetic cavity in an accelerated system of reference, ” Phys. Reu., vol. 134, pp. A799A804, 1964. [9] T. C. Mo, “Theory of electrodynamics in media in noninertial frames and applications, ” J. Math. Phys., vol. 11, pp. 25892610, 1970.
1Gb/s, fourstate, sliding block Viterbi decoder
 IEEE J. SolidState Circuits
, 1997
"... Abstract — To achieve unlimited concurrency and hence throughput in an areaefficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach red ..."
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Cited by 28 (0 self)
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Abstract — To achieve unlimited concurrency and hence throughput in an areaefficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process. A systolic SBVD architecture is presented that combines forward and backward processing of the block interval. The architecture is demonstrated in a fourstate, R =1=2, eightlevel soft decision Viterbi decoder that has been designed and fabricated in doublemetal CMOS. The 9.21 mm 2 8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (VDD =5:0V, TA =27 C). This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For lowpower operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at VDD =1:5V, demonstrating extremely low power consumption at such high rates. Index Terms—Forward error correction, trellis codes, Viterbi decoding, Viterbi detection, Viterbi estimation. I.
Channel coding: The road to channel capacity
 Proceedings of the IEEE
, 2007
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FixedLag Smoothing using Sequential Importance Sampling
, 1999
"... In this paper we present methods for fixedlag smoothing using Sequential Importance sampling (SIS) for state space models with unknown parameters. Sequential processing using Monte Carlo simulation is an area of growing interest for many engineering and statistical applications where data arrive po ..."
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Cited by 22 (2 self)
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In this paper we present methods for fixedlag smoothing using Sequential Importance sampling (SIS) for state space models with unknown parameters. Sequential processing using Monte Carlo simulation is an area of growing interest for many engineering and statistical applications where data arrive point by point rather than in a batch. The methods presented here are related to the particle filtering ideas seen in Gordon et al. (1993), Liu and Chen (1995), Berzuini et al. (1997), Pitt and Shephard (1998) and Doucet et al. (1998). Techniques for fixedlag simulation using either the filtering density or the smoothing density are developed. In addition we describe methods for regenerating parameters of the statespace model by sampling. We are concerned in particular with problems in Digital Communication systems where offline or batchbased methods, such as Markov chain Monte Carlo (MCMC), are not well suited. The new techniques are demonstrated by application to a standard digital communications model and the performance of the various methods is compared.
A Simulation Study of Forward Error Correction in ATM Networks
 Computer Communication Review
, 1992
"... If the packet loss rate in a network is higher than the loss rate requested by an application, the transport protocol must make up for the difference in loss rate. In high bandwidth delayproduct networks the latency introduced by retransmissionbased error recovery schemes may be too high for appli ..."
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Cited by 12 (1 self)
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If the packet loss rate in a network is higher than the loss rate requested by an application, the transport protocol must make up for the difference in loss rate. In high bandwidth delayproduct networks the latency introduced by retransmissionbased error recovery schemes may be too high for applications with latency constraints. In this case, Forward Error Correction (FEC) can be used. FEC allows recovery from loss without retransmission. The amount of loss recovered strongly depends on the loss behavior of the network. FEC works best if losses are dispersed. We use simulation to study the loss behavior of an output buffered multiplexer for three different traffic scenarios. Our results show how the loss behavior of the multiplexer is affected by the traffic mix and the statistics of the sources. The more bursty the sources are the larger the loss rate and the higher the probability that losses will occur in bursts. We then investigate the effectiveness of an FEC scheme that can re...
Properties of the maximum a posteriori path estimator in hidden Markov models
 IEEE Trans. Inform. Theory
, 2006
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LDPC Codes and Convolutional Codes with Equal Structural Delay: A Comparison
"... Abstract—We compare convolutional codes and LDPC codes with respect to their decoding performance and their structural delay, which is the inevitable delay solely depending on the structural properties of the coding scheme. Besides the decoding performance, the data delay caused by the channel code ..."
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Cited by 9 (6 self)
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Abstract—We compare convolutional codes and LDPC codes with respect to their decoding performance and their structural delay, which is the inevitable delay solely depending on the structural properties of the coding scheme. Besides the decoding performance, the data delay caused by the channel code is of great importance as this is a crucial factor for many applications. Convolutional codes are known to show a good performance while imposing only a very low latency on the data. LDPC codes yield superior decoding performance but impose a larger delay due to the block structure. The results obtained by comparison will also be related to theoretical limits obtained from random coding and the sphere packing bound. It will be shown that convolutional codes are still the first choice for applications for which a very low data delay is required and the bit error rate is the considered performance criterion. However, if one focuses on a low signaltonoise ratio or if the obtained frame error rate is the base for comparison, LDPC codes compare favorably.
Review of chaos communication by feedback control of symbolic dynamics
 Int. J. Bifurcation and Chaos
, 2003
"... This paper is meant to serve as a tutorial describing the link between symbolic dynamics as a description of a chaotic attractor, and how to use control of chaos to manipulate the corresponding symbolic dynamics to transmit an information bearing signal. We use the Lorenz attractor, in the form of t ..."
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Cited by 7 (4 self)
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This paper is meant to serve as a tutorial describing the link between symbolic dynamics as a description of a chaotic attractor, and how to use control of chaos to manipulate the corresponding symbolic dynamics to transmit an information bearing signal. We use the Lorenz attractor, in the form of the discrete successive maxima map of the zvariable timeseries, as our main example. For the ¯rst time, here, we use this oscillator as a chaotic signal carrier. We review the many previously developed issues necessary to create a working control of symbol dynamics system. These include a brief review of the theory of symbol dynamics, and how they arise from the °ow of a di®erential equation. We also discuss the role of the (symbol dynamics) generating partition, the di±culty of ¯nding such partitions, which is an open problem for most dynamical systems, and a newly developed algorithm to ¯nd the generating partition which relies just on knowing a large set of periodic orbits. We also discuss the importance of using a generating partition in terms of considering the possibility of using some other arbitrary partition, with discussion of consequences both generally to characterizing the system, and also speci¯cally to communicating on chaotic signal carriers. Also, of practical importance, we review the necessary feedbackcontrol issues to force the °ow of a chaotic di®erential equation to carry a desired message. 1
A CMOS IC for Gb/s viterbi decoding: system design and VLSI implementation
 IEEE Trans. VLSI Systems
, 1996
"... used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD’s) is limited by the inherent nonlinear addcompareselect (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabrica ..."
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Cited by 6 (0 self)
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used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD’s) is limited by the inherent nonlinear addcompareselect (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC’s for high speed Viterbi decoding using the “minimized method” (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a Conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC’s produced by using 1.0 p CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude. Index Terms Channel decoding, minimized method, parallel architecture, Viterbi algorithm, Viterbi decoder, VLSI.
A Low Latency SISO with Application to Broadband Turbo Decoding
 IEEE J. SELECT. AREAS COMMUN
, 2001
"... The standard algorithm for computing the softinverse of a finitestate machine [i.e., the softin/softout (SISO) module] is the forwardbackward algorithm. These forward and backward recursions can be computed in parallel, yielding an architecture with latency ( ), where is the block size. We dem ..."
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Cited by 5 (2 self)
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The standard algorithm for computing the softinverse of a finitestate machine [i.e., the softin/softout (SISO) module] is the forwardbackward algorithm. These forward and backward recursions can be computed in parallel, yielding an architecture with latency ( ), where is the block size. We demonstrate that the standard SISO computation may be formulated using a combination of prefix and suffix operations. Based on wellknown treestructures for fast parallel prefix computations in the very large scale integration (VLSI) literature (e.g., tree adders), we propose a treestructured SISO that has latency (log 2 ). The decrease in latency comes primarily at a cost of area with, in some cases, only a marginal increase in computation. We discuss how this structure could be used to design a very high throughput turbo decoder or, more generally, an iterative detector. Various subwindowing and tiling schemes are also considered to further improve latency.