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Source-to-Source Architecture Transformation for Performance Optimization in BIP
"... Abstract—BIP (Behavior, Interaction, Priorities) is a component framework for constructing systems from a set of atomic components by using two kinds of composition operators: interactions and priorities. In this paper we present a method that transforms the interactions of a component-based program ..."
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Cited by 17 (11 self)
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Abstract—BIP (Behavior, Interaction, Priorities) is a component framework for constructing systems from a set of atomic components by using two kinds of composition operators: interactions and priorities. In this paper we present a method that transforms the interactions of a component-based program in BIP and generates a functionally equivalent program. The method is based on the successive application of three types of source-to-source transformations: flattening of components, flattening of connectors and composition of atomic components. We show that the system of the transformations is confluent and terminates. By exhaustive application of the transformations, any BIP component can be transformed into an equivalent monolithic component. From this component, efficient C code can be generated. The method combines advantages of component-based description such as clarity, incremental construction and reasoning with the possibility to generate efficient monolithic code. It has been integrated in the design methodology for BIP and it has been successfully applied to two non trivial examples described in the paper. I.
Tight WCRT analysis of synchronous C programs
- In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES’09. ACM
, 2009
"... Accurate estimation of the tick length of a synchronous pro-gram is essential for efficient and predictable implementa-tions that are devoid of timing faults. The techniques to de-termine the tick length statically are classified as worst case reaction time (WCRT) analysis. While a plethora of tech- ..."
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Cited by 15 (12 self)
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Accurate estimation of the tick length of a synchronous pro-gram is essential for efficient and predictable implementa-tions that are devoid of timing faults. The techniques to de-termine the tick length statically are classified as worst case reaction time (WCRT) analysis. While a plethora of tech-niques exist for worst case execution time (WCET) anal-ysis of procedural programs, there are only a handful of techniques for determining the WCRT value of synchronous programs. Most of these techniques produce overestimates and hence are unsuitable for the design of systems that are predictable while being also efficient. In this paper, we present an approach for the accurate estimation of the ex-act WCRT value of a synchronous program, called its tight WCRT value, using model checking. For our input speci-
Predictable multithreading of embedded applications using PRET-C
- in Proceedings of the 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE). IEEE
"... Abstract—We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multi-threading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared me ..."
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Cited by 14 (3 self)
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Abstract—We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multi-threading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory communications between concurrent threads that is guaranteed to be thread safe. Due to the proposed synchronous semantics, the mapping of logical time to physical time can be achieved much more easily than with plain C, thanks to a Worst Case Reaction Time (WCRT) analyzer (not presented here). Associated to the PRET-C programming language, we present a dedicated target architecture, called ARPRET, which combines a hardware accelerator associated to an existing softcore processor. This allows us to improve the throughput while preserving the pre-dictability. With extensive benchmarking, we then demonstrate that ARPRET not only achieves completely predictable execution of PRET-C programs, but also improves the throughput when compared to the pure software execution of PRET-C. The PRET-C software approach is also significantly more efficient in comparison to two other light-weight concurrent C variants (namely SC and Protothreads), as well as the well-known Esterel synchronous programming language. I.
Building timing predictable embedded systems
- ACM Trans. Embed. Comput. Syst
, 2014
"... A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements ..."
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Cited by 6 (1 self)
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A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summa-rize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of “predictability”, and present predictability concerns at dif-ferent abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.
Scalable and Precise Refinement of Cache Timing Analysis via Model Checking
"... Abstract—Hard real time systems require absolute guarantees in their execution times. Worst case execution time (WCET) of a program has therefore become an important problem to address. However, performance enhancing features of a processor (e.g. cache) make WCET analysis a difficult problem. In thi ..."
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Cited by 4 (2 self)
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Abstract—Hard real time systems require absolute guarantees in their execution times. Worst case execution time (WCET) of a program has therefore become an important problem to address. However, performance enhancing features of a processor (e.g. cache) make WCET analysis a difficult problem. In this paper, we propose a novel approach of combining abstract interpretation and model checking for different varieties of cache analysis ranging from single to multi-core platforms. Our modeling is used to develop a precise yet scalable timing analysis method on top of the Chronos WCET analysis tool. Experimental results demonstrate that we can obtain significant improvement in precision with reasonable analysis time overhead. I.
Improving Timing Analysis For Matlab Simulink/Stateflow
- MODELS'09 ACES-MB WORKSHOP PROCEEDINGS
, 2009
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Context-Sensitive Timing Analysis of Esterel Programs
"... Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software – e.g., into sequential C code – very conservative estimation techniques have been used, where the focus has only been on obtaining safe timi ..."
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Cited by 3 (0 self)
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Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software – e.g., into sequential C code – very conservative estimation techniques have been used, where the focus has only been on obtaining safe timing estimates and not on the cost of the implementation. While this was acceptable in avionics, efficient implementations and hence tight timing estimates are needed in more cost-sensitive application domains. Lately, a number of advances in Worst-Case Execution Time (WCET) analysis techniques, coupled with the growing use of software in domains such as automotives, have led to a considerable interest in timing analysis of code generated from Esterel specifications. In this paper we propose techniques to obtain tight estimates on the processing time of input events by sequential C code generated from Esterel programs. Execution of an Esterel program – as in all other synchronous languages – is logically made up of a sequence of clock ticks. In reality, they take non-zero time which depends on the generated C code as well as the underlying hardware platform on which this code is executed. Apart from exploiting the specific structure of this C code to obtain tight WCET estimates, we capture program-level contexts across ticks in order to obtain tight estimates on response times of events whose processing spans across multiple clock ticks. Such tighter estimates immediately translate into more cost-effective implementations. Our experimental results with realistic case studies show 30 % reduction in timing estimates when program level context information is taken into account.
F.: Timing analysis enhancement for synchronous program
- In: Proceedings of the 21st International Conference on Real-Time Networks and Systems. RTNS’13
, 2013
"... In real-time systems, an upper-bound on the execution time is mandatory to guarantee all timing constraints: a bound on the Worst-Case Execution Time (WCET). High-level syn-chronous approaches are usually used to design hard real-time systems and specifically critical ones. Timing analysis used for ..."
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Cited by 1 (0 self)
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In real-time systems, an upper-bound on the execution time is mandatory to guarantee all timing constraints: a bound on the Worst-Case Execution Time (WCET). High-level syn-chronous approaches are usually used to design hard real-time systems and specifically critical ones. Timing analysis used for WCET estimates are based on the executable bi-nary program. Thus, a large part of semantic information, known at the design level, is lost due to the compilation scheme (typically organized in two stages, from high-level model to C, and then binary code). In this paper, we aim at improving the estimated WCET by taking benefit from high-level information. We integrate an existing verification tool to check the feasibility of the worst-case path. Based on a realistic example, we show that there is a large possible improvement for a reasonable analysis time overhead.
Noname manuscript No. (will be inserted by the editor) Performance Debugging of Esterel Specifications
"... Abstract Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, which needs to be validated when Esterel specifications get compiled ..."
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Abstract Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, which needs to be validated when Esterel specifications get compiled to real implementations (such as C code). In this work, we present a model-driven and architecture-aware timing analysis framework for C code generated from Esterel and executed on general-purpose processors. By integrating model-level information into the traditional timing analysis, we can efficiently compute accurate time estimates via systematically eliminating a large number of infeasible paths in the generated code. Experimental results show that with our proposed intermediate representation level infeasible path analysis in the model compilation, we obtain up to 16.1 % tighter WCET estimates compared to the traditional assembly code level infeasible path detection with substantially less analysis time. Furthermore, by maintaining the traceability links between Esterel specifications and the generated C code, we are able to map the time-critical computations at the C-level back to the Esterel-level.
DOI: 10.1109/MEMCOD.2010.5558636 Predictable multithreading of embedded applications using PRET-C
, 2013
"... We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multithreading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory commu ..."
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We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multithreading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory communications between concurrent threads that is guaranteed to be thread safe. Due to the proposed synchronous semantics, the mapping of logical time to physical time can be achieved much more easily than with plain C, thanks to a Worst Case Reaction Time (WCRT) analyzer (not presented here). Associated to the PRET-C programming language, we present a dedicated target architecture, called ARPRET, which combines a hardware accelerator associated to an existing softcore processor. This allows us to improve the throughput while preserving the predictability. With extensive benchmarking, we then demonstrate that ARPRET not only achieves completely predictable execution of PRET-C programs, but also improves the throughput when compared to the pure software execution of PRET-C. The PRET-C software approach is also significantly more efficient in comparison to two other light-weight concurrent C variants (namely SC and Protothreads), as well as the well-known Esterel synchronous programming language. 1.
