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BDS: A BDD-Based Logic Optimization System (2002)

by C Yang, M Ciesielski
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An algorithm for bi-decomposition of logic functions

by Alan Mishchenko - Proc. DAC '01 , 2001
"... We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don’t-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists a ..."
Abstract - Cited by 53 (19 self) - Add to MetaCart
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don’t-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably nonredundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time. 1.
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...wed; the more don’t-cares, the more efficient is the algorithm. According to the above classification, the closest matches to our algorithm are its previous versions [6,7,8,9] and the recent approach =-=[10,11]-=-. As evidenced by our experiments, the present version of the algorithm outperforms its previous versions and compares favorably to [10,11]. A more detailed analysis of the differences of these approa...

ABC: An Academic Industrial-Strength Verification Tool

by Robert Brayton, Alan Mishchenko
"... Abstract. ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of ..."
Abstract - Cited by 52 (14 self) - Add to MetaCart
Abstract. ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
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...ore-traditional representations in logic synthesis. As a result of our experiments with MVSIS, we developed a methodology for tackling problems, which are traditionally solved with SOPs [35] and BDDs =-=[37]-=-, using a combination of random/guided simulation of AIGs and Boolean satisfiability (SAT) [25].Based on AIGs as a new efficient representation for large logic cones, and SAT as a new way of solving ...

Fast Heuristic Minimization of Exclusive-Sums-of-Products

by Alan Mishchenko, Marek Perkowski , 2001
"... Exclusive-Sums-Of-Products (ESOPs) play an important role in logic synthesis and design-for-test. This paper presents an improved version of the heuristic ESOP minimization procedure proposed in [1,2]. The improvements concern three aspects of the procedure: (1) computation of the starting ESOP cove ..."
Abstract - Cited by 37 (2 self) - Add to MetaCart
Exclusive-Sums-Of-Products (ESOPs) play an important role in logic synthesis and design-for-test. This paper presents an improved version of the heuristic ESOP minimization procedure proposed in [1,2]. The improvements concern three aspects of the procedure: (1) computation of the starting ESOP cover; (2) increase of the search space for solutions by applying a larger set of cube transformations; (3) development of specialized datastructures for robust manipulation of ESOP covers. Comparison of the new heuristic ESOP minimizer EXORCISM-4 with other minimizers (EXMIN2 [3], MINT [4], EXORCISM-2 [1] and EXORCISM3 [2]) show that, in most cases, EXORCISM-4 produces results of comparable or better quality on average ten times faster.

Faster SAT and Smaller BDDs via Common Function Structure

by Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah - University of Michigan , 2001
"... The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techn ..."
Abstract - Cited by 26 (8 self) - Add to MetaCart
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponential in the worst-case, the structure of real-world instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as pre-processing with arbitrary SAT solvers and BDD packages without source code modifications. Finding a better variable-ordering is a well recognized problem for both SAT solvers and BDD packages. Currently, all leading edge variable-ordering algorithms are dynamic, in the sense that they are invoked many times in the course of the “host ” algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variable-sifting during BDD manipulations. In this work we propose a universal variable-ordering MINCE (MIN Cut Etc.) that pre-processes a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLCS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from real-world applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing techniques by a factor of two or more. Our results motivate search for stronger dynamic ordering heuristics and combined static/dynamic techniques. 3 1

A new enhanced constructive decomposition and mapping algorithm

by Alan Mishchenko, Xinning Wang, Timothy Kam - Proc. DAC '03
"... Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Library-aware constructive decomposition offers a solution to this problem. This paper proposes novel techniques to improve the quality and runtime of constructive decomposition. The i ..."
Abstract - Cited by 24 (13 self) - Add to MetaCart
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Library-aware constructive decomposition offers a solution to this problem. This paper proposes novel techniques to improve the quality and runtime of constructive decomposition. The improvements are effective both in the stand-alone mapping procedure and in the context of re-synthesis applied to a mapped multi-level network. Experiments with public and proprietary benchmarks show promising results.
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...work include extending re-synthesis framework tosincorporate more accurate delay modeling and physical designsaspects as well as integrating constructive decomposition with bidecomposition [5][19][27]=-=[28]-=- techniques.s10. ACKNOWLEDGEMENTSsThe first author has been supported by a research grant from IntelsCorporation. The authors thank Robert Brayton, Tsutomu Sasao,sand Marek Perkowski for illuminating ...

Constructive multi-level synthesis by way of functional properties

by Victor Nikolayevich Kravets - Ph.D. dissertation, Comput. Sci. Eng., Univ. Michigan, Ann Arbor , 2001
"... ii ..."
Abstract - Cited by 19 (2 self) - Add to MetaCart
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...ches, they do not extend easily to a library-specific synthesis. A number of approaches have also been developed which explore the structure of the decision diagram representation of a given function =-=[8, 41, 122, 124]-=-. The close relation between BDDs and multiplexer circuits has also lead to several approaches to synthesis of pass transistor logic (PTL) [7, 12, 30, 75]; they are primarily based on a mapping of (de...

Average Path Length of Binary Decision Diagrams

by Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura - IEEE TRANSACTIONS ON COMPUTERS , 2005
"... The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by a ..."
Abstract - Cited by 16 (3 self) - Add to MetaCart
The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special significance when BDDs are used in simulation and design verification. A main result of this paper is that the APL for benchmark functions is typically much smaller than for random functions. That is, for the set of all functions, we show that the average APL is close to the maximum path length, whereas benchmark functions show a remarkably small APL. Surprisingly, however, typical functions do not achieve the absolute maximum APL. We show that the parity functions are unique in having that distinction. We show that the APL of a BDD can vary considerably with variable ordering. We derive the APL for various functions, including the AND, OR, threshold, Achilles’ heel, and certain arithmetic functions. We show that the unate cascade functions uniquely achieve the absolute minimum APL.

Mince: A static global variable-ordering for sat and bdd

by Fadi A Aloul , Igor L Markov , Karem A Sakallah - in IWLS , 2001
"... Abstract ..."
Abstract - Cited by 14 (0 self) - Add to MetaCart
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Timing-Driven Logic Bi-Decomposition

by Jordi Cortadella , 2003
"... An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expre ..."
Abstract - Cited by 12 (1 self) - Add to MetaCart
An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bi-decomposition of Boolean functions and tree-height reduction of Boolean expressions. It is a technology-independent approach that enables one to find tree-like expressions with smaller depths than the ones obtained by state-of-the-art techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.

Functionally linear decomposition and synthesis of logic circuits for FPGAs

by Tomasz S. Czajkowski, Stephen D. Brown - IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
"... Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, ..."
Abstract - Cited by 7 (1 self) - Add to MetaCart
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
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...as effective in reducing the area of arithmetic, error correcting and symmetrical functions. Recently, XOR based decompositions were addressed by using Davio expansions [10] and with the help of BDDs =-=[5, 6]-=-. With Davio expansions Reed-Muller logic equation can be generated for a function, utilizing XOR gates. The idea behind using BDDs was to look for x-dominators in a BDD that indicate a presence of an...

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