A CMOS-based logic cell for the implementation of self-checking FPGAs (0)

by P Lala, A Singh, A Walker
Venue:in Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems
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Defect Tolerance at the End of the Roadmap

by Mahim Mishra, Seth C. Goldstein - IN ITC , 2004
"... Defect tolerance will become more important as feature sizes shrink closer to single digit nanometer dimensions. This is true whether the chips are manufactured using topdown methods (e.g., photolithography) or bottom-up methods (e.g., chemically assembled electronic nanotechnology, or CAEN). In thi ..."
Abstract - Cited by 26 (1 self) - Add to MetaCart
Defect tolerance will become more important as feature sizes shrink closer to single digit nanometer dimensions. This is true whether the chips are manufactured using topdown methods (e.g., photolithography) or bottom-up methods (e.g., chemically assembled electronic nanotechnology, or CAEN). In this paper, we propose a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. Our methodology is particularly well suited for CAEN.