The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques. 1: Introduction Asynchronous VLSI designs may have advantages over their synchronous counterparts. The clock skew problem no longer exists in asynchronous circuits since they do not use global clocks. In addition, asynchronous circuits have a potential for lower power consumption [1-3]. An asynchronous version of the ARM6 microprocessor (AMULET1)...

An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a twophase signalling protocol, and the latest release of the AMULET2e embedded controller, implemented using fourphase signalling, have proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BILBO registers of a doubled size.

Abstract — Asynchronous design offers a solution to the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is shown to be applicable for a wide range of implementations. Based on the C-element testability, a partial scan technique was developed that achieves a test coverage of over 99.5 % when applied to an asynchronous, networkon-chip, interconnect fabric. Test patterns are automatically generated by a custom program, given the interconnect topology. Area savings of at least 60 % are noted, in comparison to standard, asynchronous, full-scan LSSD methods. Index Terms — ATPG, stuck-at fault testing, scan-testing, asynchronous circuits, GALS.

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A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach. Keywords and phrases: asynchronous circuits, very large scale integration (VLSI), micropipelines, pseudo-random testing, ra...

: macros that can be embedded into synchronous circuitry was This paper presents a Scan path design to ease the controllability presented in [89LeenS]. To test the asynchronous modules a and observability of Self-timed logic. The Scan path registers synchronous scan test is presented there. In contradiction, the operate in asynchronous mode during operation and test. asynchronous machine operates under speed-independent Therefore, no synchronous test clock is necessary during the test conditions in non-test mode. In [91GuilSY] and [93SaloK] a standard mode. New test control modules provide the control sequences to cell design for testable Self-timed systems was presented with a switch between the parallel data path and the serial Scan path. In clock based synchronous Scan path using non overlapping clock addition to the data path, the control path and the bundled data cycles like LSSD. interface is integrated into the test concept. The new Scan path VLSI synthesis tools for asynchrono...