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...simulator has a cycle accurate model of an onchip memory controller attached to a DDR2-800 memory system. The memory controller maps physical addresses to ranks and banks using an XOR address mapping =-=[12]-=-. The system configurations are in Table 5. The SDRAM memory system configuration was chosen to be representative of most modern desktop and laptop systems. The DDR2-800 timing constraints [14] are in...

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...nificant performance degradations. For the SPEC2000 benchmarks running on a modern, high-performance microprocessor, over half of the time is spent stalling for loads that miss in the level-two cache =-=[28]-=-. We observe similar results in our simulations for a subset of SPEC2000 benchmarks and Sphinx, a speech recognition application [27]. Figure 1 compares the performance of a system with a realistic me...

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...n very aggressive prefetchers). To obtain performance benefit from such prefetches, their scheme can be combined with our cache insertion policy. 6.3. Cache Insertion Policy for Prefetches Lin et al. =-=[14]-=- evaluated static policies to determine the placement in cache of prefetches generated by a scheduled region prefetcher. Their scheme placed prefetches in the LRU position of the LRU stack. We found t...

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... most significant bits are the row address. Previous research has found that if the bank address is taken from bits that fall within the L2 set index, then writebacks will always cause bank conflicts =-=[10, 19]-=-. This is not an issue for such an Athlon-based system, as the set index and offset of the 256 KB, 16-way set associative cache with 64 byte lines only requires 14 bits. So, the bank address is alread...

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...e face of it, the scheme is similar to traditional data striping, banking, interleaving or pre-fetching used in computer systems [8][9][10][11]. Some other approaches that use Rambus DRAM controllers =-=[12]-=-[13] and other techniques that hide latency are described in [14][15][16][17]. However, unlike computer systems, packet switches cannot tolerate bank conflicts that occasionally allow the data to be d...

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...sses are mapped to multiple DRAM channels, chips, and banks. Previous studies have shown that the choice of mapping schemes significantly affects the row buffer hit rate and memory system performance =-=[32, 33, 8]-=-.sMemory access scheduling: The memory access 1 For SDRAMs, multiple chips are grouped together to support the wide and low-speed memory bus; while for Rambus DRAMs, each chip is an independent group ...

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... writes are scheduled first until the number of outstanding writes drops below one-fourth of the memory buffer size. The memory transactions are pipelined whenever possible and XORbased mapping [29], =-=[16]-=- is used as default configuration. Table 2 shows the major simulation parameters. To estimate the power consumption of DDRx DRAM devices, we follow the Micron power calculation methodology [21], [18]....

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...00 benchmark programs and execution-driven simulations of modern computer architectures, researchers have quantitatively evaluated their execution time portions for CPU operations and memory accesses =-=[19]-=- and [31]. For example, using the SPEC CPU 2000 benchmarks on a simulated 1.6 GHz, 4-way issue, out-of-order core with 64 KB split L1 caches, a 1 MB on-chip L2 cache, and an infinitely large main memo...

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...or the time to access a packet, similar to interleaving or pre-fetching used in computer systems [13][14][15][16][17]. Examples of implementations that use commercially available DRAM controllers are =-=[18]-=-[19]. While statistical guarantees might be acceptable for a computer system (in which we are used to cache misses, TLB misses, and memory refresh), it is not generally acceptable in a router where pi...