Abstruet-The problem of allocating network resources to the users of an integrated services network is investigated in the context of rate-based flow control. The network is assumed to be a virtual circuiq comection-based packet network. We show that the use of Generalized processor Sharing (GPS), when combined with Leaky Bucket admission control, allows the network to make a wide range of worst-case performance guarantees on throughput and delay. The scheme is flexible in that d~erent users may be given widely different performance guarantees, and is efilcient in that each of the servers is work conserving. We present a practicat packet-by-packet service discipline, PGPS (first proposed by Deme5 Shenker, and Keshav [7] under the name of Weighted Fair Queueing), that closely approximates GPS. This altows us to relate ressdta for GPS to the packet-bypacket scheme in a precise manner. In this paper, the performance of a single-server GPS system is analyzed exactty from the standpoint of worst-case packet delay and burstiness when the sources are constrained by leaky buckets. The worst-case sewdon backlogs are also determined. In the sequel to this paper, these results are extended to arbitrary topology networks with multiple nodes. I.

We review some recent results regarding the problem of providing deterministic quality of service guarantees in slot-based virtual circuit switched networks. The concept of a service curve is used to partially characterize the service that virtual circuit connections receive. We find that service curves provide a convenient framework for managing the allocation of performance guarantees. In particular, bounds on end-to-end performance measures can be simply obtained in terms of service curves and burstiness constraints on arriving traffic. Service curves can be allocated to the connections, and we consider scheduling algorithms that can support the allocated service curves. Such an approach provides the required degree of isolation between the connections in order to support performance guarantees, without precluding statistical multiplexing. Finally, we examine the problem of enforcing burstiness constraints in slot-based networks.

. This paper is motivated by the need to provide per session quality of service guarantees in fast packet-switched networks. We address the problem of characterizing and designing scheduling policies that are optimal in the sense of minimizing buffer and/or delay requirements under the assumption of commonly accepted traffic constraints. We investigate buffer requirements under three typical memory allocation mechanisms which represent trade-offs between efficiency and complexity. For traffic with delay constraints we provide policies that are optimal in the sense of satisfying the constraints if they are satisfiable by any policy. We also investigate the trade-off between delay and buffer optimality, and design policies that are "good" (optimal or close to) for both. Finally, we extend our results to the case of "soft" delay constraints and address the issue of designing policies that satisfy such constraints in a fair manner. Given our focus on packet switching, we mainly concern our...

All packet switches contain packet buffers to hold packets

Consider a switching component in a packet switching network, where messages from several incoming channels arrive and are routed to appropriate outgoing ports according to a service policy. One requirement in the design of such a system is to determine the buffer storage necessary at the input of each channel and the policy for serving these buffers which will prevent buffer overflow and the corresponding loss of messages. In this paper a class of buffer service policies, called Least Time to Reach Bound (LTRB), is introduced that guarantees no overflow, and for which the buffer size required at each input channel is independent of the number of channels and their relative speeds. Further, the storage requirement is only twice the maximal length of a message in all cases, and as a consequence the class is shown to be optimal in the sense that any nonoverflowing policy requires at least as much storage as LTRB. 1 Introduction We consider a system consisting of several input channels ...

A model of a switching component in a packet switching network is considered. Packets from several incoming channels arrive and must be routed to the appropriate outgoing port according to a service policy. A task confronting the designer of such a system is the selection of policy and the determination of the corresponding input buffer requirements which will prevent packet loss. One natural choice is the Longest Queue First discipline, and a tight bound on the size of the largest buffer required under this policy is obtained. The bound depends on the channel speeds and is logarithmic in the number of channels. As a consequence, Longest Queue First is shown to require less storage than Exhaustive Round Robin and First Come First Served in preventing packet overflow. This work was done while Z. Rosberg and M. Sidi were at the IBM T. J. Watson Research Center. 1 Introduction Technological advancements have brought about new switching fabrics that can support various types of traffi...

All routers contain buffers to hold packets during times of congestion. When designing a high-capacity router (or linecard) it is challenging to design buffers because of the buffer's speed and size, both of which grow linearly with line-rate, R. With today's DRAM technology, it is barely possible to design buffers for a 40Gb/s linecard in which packets are written to (read from) memory at the rate at which they arrive (depart). Over time, the problem will get harder: Link rates will increase, line cards will connect to more lines, and buffers will get larger. Ideally, we would like a memory with the density of DRAM, and the speed of SRAM. And so some commercial routers sometimes use hybrid packet buffers built from a combination of small fast SRAM and large slow DRAM. The SRAM holds ("caches") the heads and tails of packet FIFOs, allowing arriving packets to be written quickly to the tail, and departing packets to be read quickly from the head. The large DRAMs are used for bulk storage, to hold the majority of packets in each FIFO that are neither at the head nor the tail. Because of the relatively long time to write to (or read from) the DRAMs, data is transferred between SRAM and DRAM in large fixedsize blocks, consisting of perhaps many packets at a time. A memory manager shuttles packets between the SRAM cache and the DRAM with two goals: (I) Arriving packets are written to DRAM before the SRAM overflows, and (2) Departing packets are guaranteed to be in the SRAM when it's their turn to leave. In this paper we find optimal memory managers that achieve both goals, while minimizing the size of the SRAM cache. When the delay through the buffer is minimized, the size of the SRAM cache is proportional to Q In Q, where Q is the number of FIFOs t...

A switch, or server, serves n input queues, processing messages arriving at these queues to a single output channel. At each time slot the switch can process a single message from one of the queues. The goal of a switching policy is to minimize the size of the buffers at the input queues that maintain the messages that have not yet been processed. This is a typical on-line setting in which decisions are made based on the current state without knowledge of future events. This general scenario models multiplexing tasks in various systems such as communication networks, cable modem systems, and traffic control. Traditionally, researchers analyzed the performance of a given policy assuming some distribution on the arrival rates of messages at the input queues, or by assuming that the service rate is at least the aggregate of all the input rates. We use competitive analysis to analyze switching service policies, thus avoiding any prior assumptions on the input. Specifically, we show O(log n)-competitive switching policies for the problem and demonstrate matching lower bounds.

Shared memory is commonly used to build output queued (OQ) switches. An OQ switch is known to maximize throughput, minimize delay and can offer QoS guarantees. However it is generally believed that high capacity switches cannot be built from shared memory switches because the requirements on the memory size, memory bandwidth and memory access time increase linearly with the line rate and the number of ports . In this paper, we ask the following question: Is it possible to build a highspeed shared memory switch in which the individual memories (in this case, DRAMs) operate at slower than the line rate? We show that this is indeed possible i.e. a shared memory switch with a specific "conflict free DRAM memory management algorithm" (CFDMMA) can emulate a first-come-first-served OQ switch if each memory operates at a rate of approximately , where is the number of DRAMs used in parallel. We also show