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Abstract: We propose a framework for embedding model predictive control for Systems-on-a-Chip applications. In order to allow the implementation of such a computationally expensive controller on chip, we propose reducing the precision of the operations coupled with using logarithmic number system arithmetic. Two particular control problems are examined. We provide the methodology for choosing the design parameters; we emulate the performance of the embedded controller for the examined cases and we give the microprocessor architecture details. Keywords: Embedded Systems, Model Predictive Control, Systems-on-a-Chip. 1.

This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This architecture provides a small ROM-less adder/subtracter, with longer operation latency than other LNStechniques, but easily pipelineable. These characteristics make it very adequate for implementing the datapath of custom MPC embeddable microprocessors. A review of the arithmetic customization process is presented, including: an analysis of the finite precision problem, modifications to the standard MPC algorithm that simplify embedding the application, and the reasons that suggest better performance of LNSover standard floating-point (FP) architectures. The proposed arithmetic unit architecture for 16-bit LNSis fully synthesized for ASIC, and compared with an equivalent FP implementation. Area and clock cycle estimates are compared. Finally, considerations on low-precision implementations of LNSarithmetic units are provided, and an embedded-ROM implementation of addition/subtraction in LNSis proposed and analyzed.

As an alternative to floating-point, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a non-linear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately, and show that these operations are thereby competitive with their floating-point equivalents. We then show that the average performance of the logarithmic system exceeds floating-point, in terms of both speed and accuracy.

This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a high-radix CORDIC operation. A design example comparable to single precision floating point has been

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REPRESENTING AND MANIPULATING real numbers efficiently is required in many fields of science, engineering, finance, and more. Since the early years of electronic computing, many different ways of approximating real numbers on computers have been introduced. One can cite (this list is far

The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) attractive. Addition and subtraction, though, are the bottleneck of every LNS circuit, for which there are implementation techniques that tradeoff area, latency and accuracy. This paper reviews the methods of interpolation, multipartite tables and cotransformation for LNS addition and subtraction, but special focus is given on a novel version of cotransformation, for which a new special case is identified. Synthesis results compare an already published Hardware Description Language (HDL) library for LNS arithmetic that uses only multipartite tables or 2 nd-order interpolation against a variation of the same library combined with cotransformation. Exhaustive simulation and a graphics example illustrate that the proposed library has smaller area requirements and is more accurate than the earlier library, at the cost of an increase in the latency of the hardware. Track: Programmable/re-configurable architectures (Computer Arithmetic)

The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higher-order and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of medium-precision special-purpose applications. The Complex LNS (CLNS) is a generalization of LNS which represents complex values in logpolar form. CLNS is a more compact representation than traditional rectangular methods, reducing the cost of busses and memory in intensive complex-number applications like the FFT; however, prior CLNS implementations were either slow CORDIC-based or expensive 2D-table-based approaches. This paper attempts to leverage the recent advances made in realvalued LNS units for the more specialized context of CLNS. This paper proposes a novel approach to reduce the cost of CLNS addition by re-using a conventional real-valued LNS ALU with specialized CLNS hardware that is smaller than the real-valued LNS ALU to which it is attached. The resulting ALU is much less expensive than prior fast CLNS units at the cost of some extra delay. The extra hardware added to the ALU is for trigonometricrelated functions, and may be useful in LNS applications other than CLNS. The novel algorithm proposed here is implemented using the FloPoCo library (which incorporates recent HOTBM advances in function-unit generation), and FPGA synthesis results are reported.

We present a new class of number systems, called Semi-Logarithmic Number Systems, that constitute a family of various compromises between floating-point and logarithmic number systems. This allows trade between the speed of the arithmetic operations and the size of the required tables. We give arithmetic algorithms (addition/subtraction, multiplication, division) for the Semi-Logarithmic Number Systems, and we compare these number systems to the classical floating-point or logarithmic number systems. Index Terms---Logarithmic number systems, floating-point arithmetic. ------------------------------ F ------------------------------ 1I NTRODUCTION HE floating-point number system [6] is widely used for representing real numbers in computers, but many other number systems have been proposed. Among them, one can cite: the logarithmic and sign-logarithm number systems [9], [15], [14], [17], [8], [3], [10], the level-index number system [13], [20], [21], some rational number systems [11], ...