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Customizable elliptic curve cryptosystems
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2005
"... Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple-bit s ..."
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Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster
Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF(p
- International Journal of Electronics
, 2007
"... Abstract. This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides a high performance for both RSA and Elliptic Curve Cryptography (ECC). In addition, we introduce another reco ..."
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Abstract. This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides a high performance for both RSA and Elliptic Curve Cryptography (ECC). In addition, we introduce another reconfigurability for the flip-flops in order to make the best of hardware resources. The results of FPGA implementation show that better performance is obtained for ECC on the same hardware platform.
COUPLED FPGA/ASIC IMPLEMENTATION OF ELLIPTIC CURVE CRYPTO-PROCESSOR
"... In this paper, we propose an elliptic curve key generation processor over GF(2 163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for invers ..."
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In this paper, we propose an elliptic curve key generation processor over GF(2 163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.
HW/SW codesign for accelerating public-key cryptosystems over GF(p) on the 8051 µcontroller
- In Proc. World Automation Congress (WAC’06), Special Session on Information Security and Hardware Implementations
, 2006
"... Implementing large word-length public key algorithms on small 8-bit μ-controllers is a challenge. This paper presents a hardware/software co-design solution of RSA and Elliptic Curve Cryptography (ECC) over GF(p) on a 12 MHz 8-bit 8051 μ-controller. The hardware coprocessor has a modular arithmetic ..."
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Implementing large word-length public key algorithms on small 8-bit μ-controllers is a challenge. This paper presents a hardware/software co-design solution of RSA and Elliptic Curve Cryptography (ECC) over GF(p) on a 12 MHz 8-bit 8051 μ-controller. The hardware coprocessor has a modular arithmetic logic unit (MALU) of which the digit size (d) is variable. It can be adapted to the speed and bandwidth of the μ-controller to which it is connected. The HW/SW co-design space exploration is based on the GEZEL system-level design environment. It allows the designer to find the best performance-area combination for the digit size. A case study of an FPGA implementation for a 160-bit ECC over GF(p) (ECC-160p) shows that one point multiplication can be computed 40 times faster than an optimized SW implementation with the optimized digit size, d=4. KEYWORDS: HW/SW co-design, RSA, ECC, FPGA implementation, GF(p) operations 1.
Complete addition formulas for prime order elliptic curves, available at http://eprint.iacr.org/2015/1060
"... Abstract. An elliptic curve addition law is said to be complete if it correctly computes the sum of any two points in the elliptic curve group. One of the main reasons for the increased popularity of Edwards curves in the ECC community is that they can allow a complete group law that is also relativ ..."
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Abstract. An elliptic curve addition law is said to be complete if it correctly computes the sum of any two points in the elliptic curve group. One of the main reasons for the increased popularity of Edwards curves in the ECC community is that they can allow a complete group law that is also relatively efficient (e.g., when compared to all known addition laws on Edwards curves). Such complete addition formulas can simplify the task of an ECC implementer and, at the same time, can greatly reduce the potential vulnerabilities of a cryptosystem. Unfortunately, until now, complete addition laws that are relatively efficient have only been proposed on curves of composite order and have thus been incompatible with all of the currently standardized prime order curves. In this paper we present optimized addition formulas that are complete on every prime order short Weierstrass curve defined over a field k with char(k) 6 = 2, 3. Compared to their incom-plete counterparts, these formulas require a larger number of field additions, but interestingly require fewer field multiplications. We discuss how these formulas can be used to achieve secure, exception-free implementations on all of the prime order curves in the NIST (and many other) standards. 1
State of the Art in Hardware Implementations of Cryptographic Algorithms Editor
, 2006
"... PP Restricted to other programme participants (including the Commission services) RE Restricted to a group specified by the consortium (including the Commission services) CO Confidential, only for members of the consortium (including the Commission services) ..."
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PP Restricted to other programme participants (including the Commission services) RE Restricted to a group specified by the consortium (including the Commission services) CO Confidential, only for members of the consortium (including the Commission services)
Arithmetic and Architectures for Secure Hardware Implementations of Public-Key Cryptography
, 2005
"... Proefschrift voorgedragen tot het behalen van het doctoraat in de ingenieurswetenschappen door ..."
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Proefschrift voorgedragen tot het behalen van het doctoraat in de ingenieurswetenschappen door
Low Power Elliptic Curve Digital Signature Design for Constrained Devices
"... Digital signatures represent one of the most widely used security technologies for ensuring unforgeability and non-repudiation of digital data. In this paper a reduced power dissipation of hardware Elliptic Curve Digital Signature design has been developed. Our proposed architecture is based on the ..."
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Digital signatures represent one of the most widely used security technologies for ensuring unforgeability and non-repudiation of digital data. In this paper a reduced power dissipation of hardware Elliptic Curve Digital Signature design has been developed. Our proposed architecture is based on the Globally Asynchronous Locally Synchronous (GALS) design methodology. In GALS system, modules that are not used frequently can be made to consume less power by pausing their local clocks until they are needed. Our design consists of using units that are clocked independently. The whole ECDSA design is captured using VHDL language, over the finite field GF (2163), and the Virtex IV FPGA device is used for the hardware implementation of the architecture.
Comprehensive Efficient Implementations of ECC on C54xx Family of Low-cost Digital Signal Processors
"... Abstract. Resource constraints in smart devices demand an efficient cryptosystem that allows for low power and memory consumption. This has led to popularity of comparatively efficient Elliptic curve cryptog-raphy (ECC). Prior to this paper, much of ECC is implemented on re-configurable hardware i.e ..."
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Abstract. Resource constraints in smart devices demand an efficient cryptosystem that allows for low power and memory consumption. This has led to popularity of comparatively efficient Elliptic curve cryptog-raphy (ECC). Prior to this paper, much of ECC is implemented on re-configurable hardware i.e. FPGAs, which are costly and unfavorable as low-cost solutions. We present comprehensive yet efficient implementations of ECC on fixed-point TMS54xx series of digital signal processors (DSP). 160-bit prime field ECC is implemented over a wide range of coordinate choices. This paper also implements windowed recoding technique to provide better execution times. Stalls in the programming are mini-mized by utilization of loop unrolling and by avoiding data dependence. Complete scalar multiplication is achieved within 50 msec in coordinate implementations, which is further reduced till 25 msec for windowed-recoding method. These are the best known results for fixed-point low power digital signal processor to date.
