This paper builds on a series examining models of pipelined and superscalar microprocessors and their correctness by extending them to Simulataneous Multithreaded (SMT) and Chip-Level Multithreaded (CMT) processors. SMT and CMT implementations behave, to the programmer, like separate processors (virtual in the case of SMT) that communicate by means of shared state. The timing relationships are complex: the multiple (virtual) processors effectively operate over separate clocks, that are related by their temporal relationship with the corresponding implementation and its state. This relationship is complicated by the fact that SMT processors are inherently superscalar. In practice, CMT processors are also likely to be superscalar. The existing tools for modeling microprocessors and their correctness are extended to SMT and CMT systems. The model is designed to preserve the (likely large) investment in time and effort made in developing non-SMT/CMT processor models. The model is illustated by a simple, dual-core pipelined processor example. The model also accurately reflects the inevitable presence of aspects of a SMT/CMT processor’s implementation in the programmer-visible behaviour. In response to difficulties in increasing instruction-level parallelism in pipelined and superscaler processor

In addition to decreasing latency by increasing clock speeds, modern microprocessor architects improve efficiency by employing techniques such as pipelining, multiple cores and multiple threads of execution in order to achieve superior throughput. Such processors can be modelled axiomatically using an algebraic specification language and a reductive term-rewriting system, such as Maude. In this project, I seek to create such models at varying levels of complexity. I begin with a programmer’s view of the machine and proceed to develop pipelined and multi-core models. Project Dissertation submitted to the University of Wales, Swansea