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A Survey of Power Estimation Techniques in VLSI Circuits
 IEEE Transactions on VLSI Systems
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 270 (16 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...
Towards a HighLevel Power Estimation Capability
 IEEE trans. on CAD
, 1996
"... We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With ..."
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Cited by 96 (10 self)
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We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With such early warning, the designer can explore design tradeoffs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach. y This work was supported in part by Intel Corp., Santa Clara, CA. Submitted to the IEEE Transactions on CAD, 1995. 1. Introduction The high device count and operati...
Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks
, 1998
"... Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a tech ..."
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Cited by 87 (3 self)
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Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a byproduct of this analysis, we can also determine the set of input vectors which can put the circuits in the lowpower standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits. I. Introduction The increasing ...
Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
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Cited by 42 (1 self)
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Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 32 (6 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified upfront by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flipflops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flipflops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
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Cited by 21 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
A CellBased Power Estimation in CMOS Combinational Circuits
 in Proc. IEEE/ACM International Conference on ComputerAided Design
, 1994
"... In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a CellBased Power Estimation (CBPE) method is developed to estimate the power dissipation ..."
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Cited by 13 (2 self)
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In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a CellBased Power Estimation (CBPE) method is developed to estimate the power dissipation in CMOS combinational circuits. In our technique, we first construct a modified state transition graph called STGPE to model the power consumption behavior of a logic gate. Then, according to the input signal probabilities and transition densities of the logic gate, we perform an efficient method to estimate the expected activity number of each edge in the STGPE. Finally, the energy consumption of a logic gate is calculated by summing the energy consumptions of each edge in STGPE. For a set of benchmark circuits, experimental results show that the power dissipation estimated by CBPE is on average within 10percent errors as compared to the exact SPICE simulation while the CPU time is more than two orderofmagnitudes faster. 1.
MonteCarlo Approach for Power Estimation in Sequential Circuits
, 1997
"... In this paper we present a MonteCarlo based statistical techniques for estimating power in sequential circuits. Mutually independent samples of power are generated by simulating multiple copies of the circuit. Since the approach is simulationbased, spatiotemporal correlations are automatically acc ..."
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Cited by 8 (0 self)
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In this paper we present a MonteCarlo based statistical techniques for estimating power in sequential circuits. Mutually independent samples of power are generated by simulating multiple copies of the circuit. Since the approach is simulationbased, spatiotemporal correlations are automatically accounted for. The algorithm iterates until the userspecified accuracy is achieved. Experimental results on ISCAS89 circuits show that reliable results can be obtained in considerably less time than that required by exhaustive simulation.
Estimation and Bounding of Energy Consumption in BurstMode Control Circuits
 In Proc. International Conf. Computer Aided Design (ICCAD
, 1995
"... This paper describes two techniques to quantify energy consumption of burstmode asynchronous(clockless) control circuits. The circuit specifications considered are extended burstmode specifications, and the implementations are multilevel logic implementations whose outputs are guaranteed to be f ..."
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Cited by 4 (1 self)
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This paper describes two techniques to quantify energy consumption of burstmode asynchronous(clockless) control circuits. The circuit specifications considered are extended burstmode specifications, and the implementations are multilevel logic implementations whose outputs are guaranteed to be free of any voltage glitches (hazards). Both techniques use stochastic analysis to combine a small number of simulations in order to quantify average energy per external signal transition. The first technique uses Nvalued simulation to derive mathematically tight upper and lower bounds of energy consumption. Using this technique we bound the effect of hazards under all possible operating conditions and environments for a given circuit. Additionally, to drive synthesis tools for lowpower, we propose a second technique that uses fixeddelay simulation to derive a realistic estimate of energy consumption within our derived upper and lower bounds. We demonstrate the feasibility of both these techniques on a variety of burstmode control circuits used in an industrialquality chip. Our preliminary results indicate that less than 5 % of the power of typical multilevel burstmode circuits can be attributed to hazards. 1
An Overview of LowPower Techniques for FieldProgrammable Gate Arrays
 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS
, 2008
"... This paper provides an overview of lowpower techniques for fieldprogrammable gate arrays (FPGAs). It covers systemlevel design techniques and devicelevel design techniques that have targeted current commercial devices. It also describes current research on circuitlevel and architecturelevel de ..."
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Cited by 3 (0 self)
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This paper provides an overview of lowpower techniques for fieldprogrammable gate arrays (FPGAs). It covers systemlevel design techniques and devicelevel design techniques that have targeted current commercial devices. It also describes current research on circuitlevel and architecturelevel design techniques. Recent studies on power modelling and on lowpower computeraided design (CAD) are also reported. Finally, it proposes future work that would enable the use of FPGA technology in applications where power and energy consumption is critical, such as mobile devices.