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LUT cascades and emulators for realizations of logic functions
 RM2005
, 2005
"... Two types of programmable logic devices using LUTs (LookUp Tables) are presented. An LUT cascade directly implements logic functions by a series connection of LUTs, while an emulator emulates an LUT cascade by sequentially accessing LUTs. The LUT cascade is faster, but has a limited logic capabilit ..."
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Two types of programmable logic devices using LUTs (LookUp Tables) are presented. An LUT cascade directly implements logic functions by a series connection of LUTs, while an emulator emulates an LUT cascade by sequentially accessing LUTs. The LUT cascade is faster, but has a limited logic capability, while the emulator is slower, but has a higher logic capability. LUT cascades and emulators can be directly generated from the BDDs of target functions. Their performances are easy to estimate. The Cmeasure that show the complexity of LUT cascades are also presented. Functions with small Cmeasures have efficient LUT cascade and emulator realizations. Classes of functions that are suitable for LUT cascade and emulator realizations are also presented.
On Designs of Radix Converters Using Arithmetic Decompositions
"... In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for pnary to binary converters. It introd ..."
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In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for pnary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs. 1
Design of Arbiters and Allocators Based on
"... Abstract: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decisionmaking modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computeraided technique that can produce repr ..."
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Abstract: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decisionmaking modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computeraided technique that can produce representations of arbiters/allocators in a form of a MultiTerminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multipleoutput lookup tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variableordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.
A Hybrid Logic Simulator Using LUT Cascade Emulators
"... Abstract — This paper presents a hybrid logic simulator using both an eventdriven and a cyclebased methods. For special primitives such as memories and tristate buffers, it uses an eventdriven method. For other parts, it uses a cyclebased method using LUT cascade emulators. To simulate a large ..."
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Abstract — This paper presents a hybrid logic simulator using both an eventdriven and a cyclebased methods. For special primitives such as memories and tristate buffers, it uses an eventdriven method. For other parts, it uses a cyclebased method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones, and realizes each part by an LUT cascade emulator. Next, it combines these emulators by interconnections. Since a multiplier often requires large memories in an LUT cascade, an instruction of the processor is used instead of the LUT cascade. This will reduce the code size and the simulation time. Our experiment shows that proposed method is effective for circuits including arithmetic operations. I.
Short Papers Analysis and Synthesis of WeightedSum Functions
"... Abstract—A weightedsum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by lookup table (LUT) cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, the size of LU ..."
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Abstract—A weightedsum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by lookup table (LUT) cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, the size of LUT cascades that realize WS functions can be estimated. The arithmetic decomposition of a WS function is also shown. With this method, a WS function can be implemented with cascades and adders. Index Terms—Binary decision diagram, column multiplicity, complexity of logic functions, digital filter, distributed arithmetic, field programmable gate array (FPGA), functional decomposition, LUT cascades, radix converter, symmetric function, threshold function. I.
Abstract Analysis and Synthesis of WeightedSum Functions
"... A weightedsum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by LUT cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, we can estimate the size of LUT cascade ..."
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A weightedsum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by LUT cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, we can estimate the size of LUT cascades that realize WS functions. These bounds are useful to realize WS functions, since they show strategies to partition the outputs into groups. 1
Digital Signal Processing Designing for FPGA Architectures
, 2007
"... Abstract: This paper presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeted for modern FPGA architectures. Modern programmable structures are equipped with specialized DSP embedded blocks that allow implementing digital signal processing algorithms ..."
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Abstract: This paper presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeted for modern FPGA architectures. Modern programmable structures are equipped with specialized DSP embedded blocks that allow implementing digital signal processing algorithms with use of the methodology known from digital signal processors. On the first place, however, programmable architectures give the designer the possibility to increase efficiency of designed system by exploitation of parallelism of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA) that will boost the performance of designed processing systems. Additionally, application of the functional decomposition based methods, known to be best suited for FPGA structures, allows utilizing possibilities of programmable technology in very high degree. The paper presents results of comparison of different design approaches in this area.