an iWarp cell; up to 64 MBytes of memory are directly addressable. A large array of iWarp cells will deliver an iWarp is a system architecture for high speed signal, image enormous computing bandwidth never before realized in dis- and scientific computing. The heart of an iWarp system is the iWarp component: a single chip processor that requires only tributed memory parallel systems. Because of the strong the addition of memory chips to form a complete system computation and communication capabilities and because of building block, called the iWarp cell. Each iWarp component its commercial availability, iWarp is expected to be an imporcontains both a powerful computation engine (20 MFLOPS) tant building block for a diverse set of high performance and a high throughput (320 MBytes/sec), low latency parallel systems. (100-150 ns) communication engine for interfacing with other The iWarp architecture evolved from the Warp iWarp cells. Because of its strong computation and commachine [1], ...

ABSTRACT The problem of performing multtphcaUon of n-bit binary numbers on a chip is considered Let A denote the ch~p area and T the time reqmred to perform mult~phcation. By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, ~t is shown that A T 2. for all a ~ [0, 1], where A0 and To are posmve constants which depend on the technology but are mdependent of n. The exponent 1 + a is the best possible A consequence of this result is that binary multiphcatlon is &quot;harder &quot; than binary addmon More precisely, ff(AT2~)M(n) and (AT2~)A(n) denote the mmimum area-time complexity for n-b~t binary multiphcauon and addmon, respectively, then (AT2~)M(n) _ 1 f~(nl-a) for 0 _< a--< na for ~<a_<l for°>, ( = fi(nl/2) for all a _> 0).

Dedicated to my wonderful parents, with love. ii

A straw-man proposal for a multi-mega baseline “Giant Systolic Array ” for the “X ” part of the SKA poly-phase FX correlator is investigated. A modular system with no large corner-turner, fault-tolerant, and virtually free of cables, based on the use of HM-Zd connectors and inexpensive nearest-neighbour printed wiring connections is developed and discussed. This system is flexible in allowing tradeoffs of bandwidth for number of beams as well as partial bandwidth correlation with other bandwidth-overlap SKA elements. The system can incrementally grow with SKA growth, and successive generations of technology improvements can be accommodated without replacing the system infrastructure, allowing for bandwidth and number of beam increases. Very rough cost and power estimates for a system with 1 GHz per pol’n and 81,920 channels per baseline are developed.

Dedicated to the memory of Robert Brooks, a colleague and friend Abstract. We investigate the filling area conjecture, optimal systolic inequalities, and the related problem of the nonvanishing of certain linking numbers in 3-manifolds.