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A Survey of Power Estimation Techniques in VLSI Circuits
 IEEE Transactions on VLSI Systems
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 270 (16 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...
Power minimization in IC design: principles and applications,"
 ACM Transactions on Design Automation of Electronic Systems,
, 1996
"... Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for des ..."
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Cited by 200 (31 self)
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Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
A survey of optimization techniques targeting low power circuits
 in Proc. Design Automation Conf
, 1995
"... Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I. ..."
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Cited by 77 (0 self)
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Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I.
Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design
 INTERNATIONAL SYMPOSIUM ON LOW POWER DESIGN
, 1995
"... The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. This paper describes the development and application of algorithms that use ideas s ..."
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Cited by 70 (4 self)
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The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. This paper describes the development and application of algorithms that use ideas similar to power management, but that are applicable to logic level synthesis/design. The proposed approach is termed guarded evaluation. The main idea here is to determine, on a per clock cycle basis, which parts of a circuit are computing results that will be used, and which are not. The sections that are not needed are then “shut off”, thus saving the power used in all the useless transitions in that part of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach. While this
Efficient Estimation of Dynamic Power Consumption under a Real Delay Model
 IEEE Internations Conference on ComputerAided Design
, 1993
"... In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for cmos circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition w ..."
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Cited by 49 (0 self)
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In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for cmos circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition waveforms. In particular, we approximate the correlation between transition waveforms for two signal lines by the correlation between the steady state values of these lines. We obtain an order of magnitude speed up over an exact method with an average error of only 1%. 1 Introduction With recent advances in microelectronic technology, smaller devices are now possible allowing more functionality on an integrated circuit (ic). Portable applications have shifted from conventional low performance products such as wristwatches and calculators to high throughput and computationally intensive products such as notebook computers and personal digital assistants. The new applications require high spe...
G.De Micheli, ”State assignment for low power dissipation
 Custom Integrated Circuits Conference
, 1994
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HighLevel Synthesis Techniques for Reducing the Activity of Functional Units
, 1995
"... Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during highlevel synthesis (highlevel transformations, scheduling and binding). Several t ..."
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Cited by 42 (1 self)
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Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during highlevel synthesis (highlevel transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switchlevel simulations show that significant improvements can be achieved.
Gatelevel Power Estimation Using Tagged Probabilistic Simulation
"... In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagg ..."
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Cited by 42 (1 self)
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In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. From the tagged waveform, one can calculate the switching activity and hence the average power consumption of the circuit node. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 23 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits
 ACM/IEEE 31st Design Automation Conference
, 1994
"... We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% o ..."
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Cited by 39 (1 self)
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We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% of the exact ChapmanKolmogorov method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. 1 Introduction The average power dissipation of a circuit, like its area or speed, may be significantly improved by changing the architecture or the technology of the circuit. But once these architectural or technological improvements have been made, it is the switching of the logic that will ultimately determine its power dissipation. Methods for the power estimation of logiclevel combinational circuits based on switching activity estimation (e.g. [2], [4]) have been presented previously. Power ...
Techniques for the Power Estimation of Sequential Logic Circuits Under UserSpecified Input Sequences and Programs
 IEEE Transactions on VLSI Systems
, 1994
"... We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or proc ..."
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Cited by 38 (9 self)
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We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how userspecified sequences and programs can be modeled using a finite state machine, termed an inputmodeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit. I. INTRODUCTION Average power dissipation estimation is...