Results 1  10
of
38
Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
Abstract

Cited by 197 (28 self)
 Add to MetaCart
Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
Abstract

Cited by 106 (12 self)
 Add to MetaCart
(Show Context)
Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
A survey of optimization techniques targeting low power circuits
 in Proc. Design Automation Conf
, 1995
"... Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I. ..."
Abstract

Cited by 77 (0 self)
 Add to MetaCart
(Show Context)
Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I.
Gatelevel Power Estimation Using Tagged Probabilistic Simulation
"... In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagg ..."
Abstract

Cited by 42 (1 self)
 Add to MetaCart
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. From the tagged waveform, one can calculate the switching activity and hence the average power consumption of the circuit node. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 23 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
HighLevel power modeling of CPLDs and FPGAs
 In Proceedings of the International Conference on Computer Design
, 2001
"... In this paper, we present a highlevel power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and fieldprogrammable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we ..."
Abstract

Cited by 24 (2 self)
 Add to MetaCart
(Show Context)
In this paper, we present a highlevel power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and fieldprogrammable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use an adaptive regression method to model the FPGA power consumption. Such a highlevel model can be used in the inner loop of a systemlevel synthesis tool to estimate the power consumed by different FPGA resources for different potential systemlevel synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our highlevel power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1 % compared to lowlevel FPGA power simulation methods. 1.
Stochastic Sequential Machines Synthesis with Application to Constrained Sequence Generation
, 1996
"... ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM Inc., 1515 Broadway, New York, ..."
Abstract

Cited by 22 (13 self)
 Add to MetaCart
(Show Context)
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 8690481, or permissions@acm.org. 1996 by the Association for Computing Machinery, Inc. 2 1. Introduction In the past, time, area and testability were the primary concerns of IC designers. With the growing need for lowpower electronic circuits and systems, power estimation and lowpower optimization have become crucial tasks that must be also addressed. It is expected that, in the forthcoming years, power issues will receive increasing attention due to the widespread use of portable applications and desire to reduce the packaging and cooling costs of highend systems. Power estimation techniques must be fast and accurate in order to be applicable in practice. ...
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
Abstract

Cited by 21 (0 self)
 Add to MetaCart
(Show Context)
With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.
Adaptive models for input data compaction for power simulators," To appear
 in Proceedings of the 2nd AsiaPaci c Design Automation Conference
, 1997
"... Abstract This paper presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this pape ..."
Abstract

Cited by 20 (11 self)
 Add to MetaCart
Abstract This paper presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this paper introduces and characterizes a family of dynamic Markov trees that can model complex spatiotemporal correlations which occur during power estimation both in combinational and sequential circuits. As the results demonstrate, large compaction ratios of 12 orders of magnitude can be obtained without significant loss (less than 5% on average) in the accuracy of power estimates. I.
Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation
, 1997
"... We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods th ..."
Abstract

Cited by 17 (3 self)
 Add to MetaCart
We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods that estimate switching activity, our method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals.
Design Technologies for Low Power VLSI
 In Encyclopedia of Computer Science and Technology
, 1997
"... Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing l ..."
Abstract

Cited by 16 (0 self)
 Add to MetaCart
(Show Context)
Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.