The first step towards the design of video processors and video systems is to achieve an accurate understanding of the major video applications, including not only the fundamentals of the many video compression standards, but also the workload characteristics of those applications. Introduced in 1997, the MediaBench benchmark suite provided the first set of full application-level benchmarks for studying video processing characteristics, and has consequently enabled significant research in computer architecture and compiler research for multimedia systems. To expedite the next generation of systems research, the MediaBench Consortium is developing the MediaBench II benchmark suite, incorporating benchmarks from the latest multimedia technologies, and providing both a single composite benchmark suite as well as separate benchmark suites for each area of multimedia. In the area of video, MediaBench II Video includes both the popular mainstream video compression standards, such as Motion-JPEG, H.263, and MPEG-2, and the more recent next-generation standards, including MPEG-4, Motion-JPEG2000, and H.264. This paper introduces MediaBench II Video and provides a comprehensive workload evaluation of its major processing characteristics.

Novel algorithmic features of multimedia applications and advances in VLSI technologies are driving forces behind the new multimedia signal processors. We propose an architecture platform which could provide high performance and flexibility,andwould require less external I/O and memory access. It is comprised of array processors to be used as the hardware accelerator and RISC cores to be used as the basis of the programmable processor. It is a hierarchical and scalable architecture style which facilitates the hardware-software codesign of multimedia signal processing circuits and systems. While some controlintensive functions can be implemented using programmable CPUs, other computation-intensive functions canrelyonhardware accelerators.

lack the flexibility to accommodate to algorithm modifications, and the large design effort justifies a dedicated implementation only for high-volume consumer market products of fixed functionality. Alternatively, programmable approaches offer a higher degree of flexibility. In order to attain MSP performance, architectural strategies for programmable processors are based on parallelization and adaptation principles. Several alternatives exist to exploit the parallelization potential of MSP algorithms for programmable architectures: Aiming at data parallelism, SIMD (Single Instruction Stream, Multiple Data Streams) architectures are characterized by several data paths executing the same operation on different data entities in parallel. While thus a high degree of parallelism can be achieved with little control overhead, data path utilization rapidly decreases for scalar program parts. In general, pure SIMD architectures are not an efficient solution for complex multimedia applicatio

In the development of video and multimedia standards, new algorithms often result from the need to improve the efficiency or to reduce the cost of implementation. On the other hand, new implementation techniques are often triggered by algorithms that are too computation intensive with existing technology. Therefore, in multimedia applications, the development of algorithms and the progrless in architectures are closely tied to each other. In this paper, we will introduce a number of new video and multimedia standards and discuss special implementation considerations demanded by these new standards. 1.