Results 1 -
7 of
7
Application specific network-on-chip design with guaranteed quality approximation algorithms
- in Proc. ASPDAC, 2007
"... Abstract—Network-on-Chip (NoC) architectures with opti-mized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multi-processor System-on-Chip (MPSoC) devices. The application spe-cific NoC design problem takes as input the system-level floorpl ..."
Abstract
-
Cited by 6 (1 self)
- Add to MetaCart
(Show Context)
Abstract—Network-on-Chip (NoC) architectures with opti-mized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multi-processor System-on-Chip (MPSoC) devices. The application spe-cific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with integer linear programming (ILP) formulations, and heuristic techniques. I.
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
"... Abstract—This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target de-vice. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synt ..."
Abstract
-
Cited by 6 (0 self)
- Add to MetaCart
(Show Context)
Abstract—This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target de-vice. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis ap-proach consisting of the following: 1) core to router mapping and 2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage 1)] and a factor-2 approximation algorithm for custom topology generation [stage 2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by compar-isons with existing approaches. Index Terms—Application specific integrated circuit (ASIC), approximation methods, design automation, network-on-chip. I.
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique
"... Abstract—The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection ar-chitecture that can support the communication requirements for the SoC with the desired performance. This paper presents a ge-netic algorithm-based automated design techniqu ..."
Abstract
-
Cited by 4 (0 self)
- Add to MetaCart
Abstract—The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection ar-chitecture that can support the communication requirements for the SoC with the desired performance. This paper presents a ge-netic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communica-tion traces on the interconnection network. The technique oper-ates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimen-tation with benchmark applications and comparisons with existing approaches. Index Terms—Design automation, genetic algorithms, net-work-on-chip (NoC), routing. I.
An ILP Formulation for System-Level Application Mapping on Network Processor Architectures
, 2007
"... Current day network processors incorporate several architec-tural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique fo ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
(Show Context)
Current day network processors incorporate several architec-tural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. We present an automated system-level design technique for application devel-opment on such architectures. The technique incorporates pro-cess transformations and block multi-threading aware data map-ping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental re-sults that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architec-ture. The results demonstrate that our technique is able to gen-erate high-quality mappings of realistic applications on the target architecture within a short time.
allocation in Chip Multiprocessor (CMP)-based
"... Abstract—This work tries to derive ideas for thread ..."
2B-5 Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
"... Abstract — Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorpla ..."
Abstract
- Add to MetaCart
(Show Context)
Abstract — Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with integer linear programming (ILP) formulations, and heuristic techniques. I.
Contents lists available at ScienceDirect Parallel Computing
"... journal homepage: www.elsevier.com/locate/parco Thread allocation in CMP-based multithreaded network processors ..."
Abstract
- Add to MetaCart
journal homepage: www.elsevier.com/locate/parco Thread allocation in CMP-based multithreaded network processors
