Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing new processor architectures, as well as when evaluating the performance of new processor enhancements. However, despite this dependence on simulators, statistically rigorous simulation methodologies are not typically used in computer architecture research. A formal methodology can provide a sound basis for drawing conclusions gathered from simulation results by adding statistical rigor, and consequently, can increase confidence in the simulation results. This paper demonstrates the application of a rigorous statistical technique to the setup and analysis phases of the simulation process. Specifically, we apply a Plackett and Burman design to: 1) identify key processor parameters, 2) classify benchmarks based on how they affect the processor, and 3) analyze the effect of processor performance enhancements. Our technique expands on previous work by applying a statistical method to improve the simulation methodology instead of applying a statistical model to estimate the performance of the processor.

: This paper describes a prototype implementation of a dynamic bandwidth allocation service for ATM-based networks. The major purpose of this service is to increase resource utilization in a network supporting multimedia applications. The implementation was made using API (Application User Interface) compatible with UNI version 3.0. The implementation consists of a set of primitives and their related PDUs (Protocol Data Units). Some measurements were done using the prototype implementation in order to observe the behavior of renegotiation rejections with respect to some parameters, such as node capacity, level of reservations, number of nodes and so on. The results here shown that dynamic bandwidth allocation service can be used to increase resource utilization and, at the same time, to provide a high level of guarantee to the accepted connections. Keywords: Quality of Service, ATM and Multimedia Applications 1. Introduction Resource allocation in high speed networks is one of the m...

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Manufacturers using traditional process control charts to monitor their sheet metal stamping processes often encounter out-of-control signals indicating that the process mean has changed. Unfortunately, a sheet metal stamping process does not have the necessary adjustability in its process variable input settings to allow adjusting the mean response in an out-of-control condition, hence the signals often go ignored. Accordingly, manufacturers are unaware how much these changes in the mean inflate the variance in the process output. We suggest using a designed experiment to quantify the variation in stamped panels attributable to changing means. Specifically, we suggest classifying stamping variation into three components: part-to-part, batch-to-batch, and within batch variation. The part-to-part variation represents the short run variability about a given stable or trending batch mean. The batch-to-batch variation represents the variability of the individual batch mean between die setups. The within batch variation represents any movement of the process mean during a given batch run. Using a twofactor nested analysis of variance model, a manufacturer may estimate the three components of variation. After partitioning the variation, the manufacturer may identify appropriate

Sec. 300.1 Purpose and objectives.

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To reduce the simulation time to a tractable amount or due to compilation (or other related) problems, computer architects often simulate only a subset of the benchmarks in a benchmark suite. However, if the architect chooses a subset of benchmarks that is not representative, the subsequent simulation results will, at best, be misleading or, at worst, yield incorrect conclusions. To address this problem, computer architects have recently proposed several statistically-based approaches to subset a benchmark suite. While some of these approaches are well-grounded statistically, what has not yet been thoroughly evaluated is the: 1) Absolute accuracy, 2) Relative accuracy across a range of processor and memory subsystem enhancements, and 3) Representativeness and coverage of each approach for a range of subset sizes. Specifically, this paper evaluates statistically-based subsetting approaches based on principal components analysis (PCA) and the Plackett and Burman (P&B) design, in addition to prevailing approaches such as integer vs. floating-point, core vs. memory-bound, by language, and at random. Our results show that the two statistically-based approaches, PCA and P&B, have the best absolute and relative accuracy for CPI and energy-delay product (EDP), produce subsets that are the most representative, and choose benchmark and input set pairs that are most well-distributed across the benchmark space. To achieve a 5 % absolute CPI and EDP error, across a wide range of configurations, PCA and P&B typically need about 17 benchmark and input set pairs, while the other five approaches often choose more than 30 benchmark and input set pairs.