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Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
"... Abstract. Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, ..."
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Cited by 6 (3 self)
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Abstract. Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear constraints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implementations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
- In Proc. FORMATS’06, volume 4202 of LNCS
, 2006
"... Abstract. Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different impl ..."
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Cited by 6 (5 self)
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Abstract. Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.
Case Studies Using Imitator II
, 2010
"... Timed automata [1] are finite control automata equipped with clocks, which are real-valued variables which increase uniformly. This model is useful for reasoning about real-time systems with a dense representation of time, because one can specify quantitatively the interval of time during which the ..."
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Timed automata [1] are finite control automata equipped with clocks, which are real-valued variables which increase uniformly. This model is useful for reasoning about real-time systems with a dense representation of time, because one can specify quantitatively the interval of time during which the transitions can occur,
Formal Timing Analysis of Full-Custom Memory Circuits
"... Abstract — Embedded SRAM are key bricks for system on chip performances. The competition is keen for IP providers. Thus, the timing margins must be reduced in order to release extra performances to the customers. Today, the verification is mainly based on spice simulations which are very accurate, b ..."
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Abstract — Embedded SRAM are key bricks for system on chip performances. The competition is keen for IP providers. Thus, the timing margins must be reduced in order to release extra performances to the customers. Today, the verification is mainly based on spice simulations which are very accurate, but very slow and with a limited coverage. Our strategy is then to combine transistor abstraction with timings and parametric formal verification techniques. We illustrate our methodology on a portion of a commercial embedded memory and show how it can be used to improve the product datasheet. Moreover, the automated generation of the design constraint equations is an innovative approach to help designers with performances improvement. I.
Task T4- Livrables D4.2 and D4.3- established at T0 + 48 Experiments of Prototype Tools on Case Studies, Comparison of obtained results and Conclusion
"... This document is a merge of livrables D4.2 ”Experiments of Prototype Tools on Cases Studies ” and D4.3 ”Comparison of obtained results and Conclusion ” in the initial proposition. It concludes the VALMEM project by applying the set of tools developed during the project to (some of) the case studies ..."
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This document is a merge of livrables D4.2 ”Experiments of Prototype Tools on Cases Studies ” and D4.3 ”Comparison of obtained results and Conclusion ” in the initial proposition. It concludes the VALMEM project by applying the set of tools developed during the project to (some of) the case studies defined initially. The obtained results are discussed and compared with standard methodologies outcomes. In the initial proposition, these two documents were separated since we planned to apply our flow to several case studies (SPSMALL memory, SPREG memory, including self-timed logics). At the end of the project, we were able to apply it to the SPSMALL memory, but the particular mechanisms of SPREG have not been introduced into the preliminary stages of our flow. Hence we found preferable to merge the two documents into a unique one. This document is structured as follows: the first part recalls our method-ological flow. Parts 2 to 6 describe the application of this flow to SPSMALL memory. The architecture and specificities of SPSMALL are recalled in section 2; abstraction and timing extraction are applied in section 3; formal analysis performed by timed-model checking and parametric timed model-checking are reported into sections 4 and 5. Encountered and remaining difficulties are com-mented in section 6. Comparisons and conclusions are drawn in section 7. 1 Analysis Flow of full custom memory proposed in the VALMEM project The Functional and Timing analysis problem we concentrate on can be expressed in the following way. Given: – a full-custom memory circuit described at transistor level, for a given tech-nology, – a specification provided by the manufacturer, describing (1) the conditions to be met by the environment (called nominal conditions), (2) the guaranteed performances of the memory (namely the access timings) assuming these nominal conditions are met. Determine: – the correctness of the access timings given in the specification, – the extremal stability periods of environment signals still guarantying the functionality and the access timings of the memory.
Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata!!!
, 2006
"... Abstract. Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing be-haviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, ..."
Abstract
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Abstract. Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing be-haviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear con-straints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implemen-tations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.
