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62
AND/OR Search Spaces for Graphical Models
, 2004
"... The paper introduces an AND/OR search space perspective for graphical models that include probabilistic networks (directed or undirected) and constraint networks. In contrast to the traditional (OR) search space view, the AND/OR search tree displays some of the independencies present in the gr ..."
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Cited by 119 (44 self)
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The paper introduces an AND/OR search space perspective for graphical models that include probabilistic networks (directed or undirected) and constraint networks. In contrast to the traditional (OR) search space view, the AND/OR search tree displays some of the independencies present in the graphical model explicitly and may sometime reduce the search space exponentially. Indeed, most
DAGaware AIG rewriting: A fresh look at combinational logic synthesis
 In DAC ’06: Proceedings of the 43rd annual conference on Design automation
, 2006
"... This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rew ..."
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Cited by 105 (33 self)
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This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technologyindependent flow is implemented in a publicdomain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1
BDS: A BDDBased Logic Optimization System
 Proc. of DAC 2000
, 2000
"... This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network e ..."
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Cited by 76 (0 self)
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This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.
An algorithm for bidecomposition of logic functions
 Proc. DAC '01
, 2001
"... We propose a new BDDbased method for decomposition of multioutput incompletely specified logic functions into netlists of twoinput logic gates. The algorithm uses the internal don’tcares during the decomposition to produce compact wellbalanced netlists with short delay. The resulting netlists a ..."
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Cited by 53 (19 self)
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We propose a new BDDbased method for decomposition of multioutput incompletely specified logic functions into netlists of twoinput logic gates. The algorithm uses the internal don’tcares during the decomposition to produce compact wellbalanced netlists with short delay. The resulting netlists are provably nonredundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDDbased decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time. 1.
Improvements to Technology Mapping for LUTbased FPGAs
 IEEE TCAD
, 2007
"... The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new t ..."
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Cited by 35 (12 self)
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The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new technique for onthefly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7 % and area by 14%, compared to DAOmap.
A new enhanced constructive decomposition and mapping algorithm
 Proc. DAC '03
"... Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to this problem. This paper proposes novel techniques to improve the quality and runtime of constructive decomposition. The i ..."
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Cited by 24 (13 self)
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Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to this problem. This paper proposes novel techniques to improve the quality and runtime of constructive decomposition. The improvements are effective both in the standalone mapping procedure and in the context of resynthesis applied to a mapped multilevel network. Experiments with public and proprietary benchmarks show promising results.
DECOMPOS: An Integrated System for Functional Decomposition
 1998 International Workshop on Logic Synthesis, Lake Tahoe
, 1998
"... This paper presents a system for disjoint decompositions of logic functions with many inputs. It is a combination of three different methods: 1) Disjoint decompositions with a few bound set variables; 2) Disjoint bidecompositions; and 3) Decompositions using Jacobian. 1) and 2) are quick, but find ..."
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Cited by 23 (7 self)
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This paper presents a system for disjoint decompositions of logic functions with many inputs. It is a combination of three different methods: 1) Disjoint decompositions with a few bound set variables; 2) Disjoint bidecompositions; and 3) Decompositions using Jacobian. 1) and 2) are quick, but find only limited classes of decompositions, while 3) finds all disjoint decompositions by spending more time. Weshow the results of decompositions for more than four thousand functions. We also define a new class of functions: Completely bidecomposable functions. Experimental results show that many practical logic functions have disjoint decompositions and some are completely bidecomposable functions. I Introduction In general, an nvariable function f requires about 2 n =n gates [23]. Suppose that the function f can be decomposed into twonetworks as shown in Fig. 1.1. Let the numbers of inputs for the network H and G be n 1 and n 2 + 1, respectively, where n 1 + n 2 = n. Then, H and ...
Simplifying Boolean constraint solving for random simulationvector generation
 In Proceedings of ICCAD 2002
, 2004
"... jun.yuan,ken.albin¡ We present an algorithm for simplifying the solution of conjunctive Boolean constraints of state and input variables, in the context of constrained random vector generation using BDDs. The basis of our approach is extraction of “holdconstraints ” from constraint system. Holdcon ..."
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Cited by 22 (4 self)
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jun.yuan,ken.albin¡ We present an algorithm for simplifying the solution of conjunctive Boolean constraints of state and input variables, in the context of constrained random vector generation using BDDs. The basis of our approach is extraction of “holdconstraints ” from constraint system. Holdconstraints are deterministic and trivially resolvable; in addition, they can be used to simplify the original constraints as well as refine the conjunctive partition. Experiments demonstrate significant reduction in the time and space needed for constructing the conjunction BDDs, and the time spent in vector generation during simulation. 1
Constructive multilevel synthesis by way of functional properties
 Ph.D. dissertation, Comput. Sci. Eng., Univ. Michigan, Ann Arbor
, 2001
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Compiling constraint networks into AND/OR multivalued decision diagrams (AOMDDs)
 IN PROCEEDINGS OF THE TWELFTH INTERNATIONAL CONFERENCE ON PRINCIPLES AND PRACTICE OF CONSTRAINT PROGRAMMING (CP’06
, 2006
"... Inspired by AND/OR search spaces for graphical models recently introduced, we propose to augment Ordered Decision Diagrams with AND nodes, in order to capture function decomposition structure. This yields AND/OR multivalued decision diagram (AOMDD) which compiles a constraint network into a canonic ..."
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Cited by 19 (4 self)
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Inspired by AND/OR search spaces for graphical models recently introduced, we propose to augment Ordered Decision Diagrams with AND nodes, in order to capture function decomposition structure. This yields AND/OR multivalued decision diagram (AOMDD) which compiles a constraint network into a canonical form that supports polynomial time queries such as solution counting, solution enumeration or equivalence of constraint networks. We provide a compilation algorithm based on Variable Elimination for assembling an AOMDD for a constraint network starting from the AOMDDs for its constraints. The algorithm uses the APPLY operator which combines two AOMDDs by a given operation. This guarantees the complexity upper bound for the compilation time and the size of the AOMDD to be exponential in the treewidth of the constraint graph, rather than pathwidth as is known for ordered binary decision diagrams (OBDDs).