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Hardware Implementation of Elliptic Curve Processor over GF(p)
 International Journal of Embedded Systems
, 2003
"... This paper describes a hardware implementation of an arithmetic processor which is efficient for bitlengths suitable for both commonly used types of Public Key Cryptography (PKC), i.e., Elliptic Curve (EC) and RSA Cryptosystems. The processor consists of special operational blocks for Montgomery Mo ..."
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Cited by 36 (6 self)
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This paper describes a hardware implementation of an arithmetic processor which is efficient for bitlengths suitable for both commonly used types of Public Key Cryptography (PKC), i.e., Elliptic Curve (EC) and RSA Cryptosystems. The processor consists of special operational blocks for Montgomery Modular Multiplication, modular addition/substraction, EC Point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.
Sign Change Fault Attacks on Elliptic Curve Cryptosystems
 Fault Diagnosis and Tolerance in Cryptography 2006 (FDTC ’06), volume 4236 of Lecture Notes in Computer Science
, 2004
"... We present a new type of fault attacks on elliptic curve scalar multiplications: Sign Change Attacks. These attacks exploit di#erent number representations as they are often employed in modern cryptographic applications. Previously, fault attacks on elliptic curves aimed to force a device to out ..."
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Cited by 27 (0 self)
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We present a new type of fault attacks on elliptic curve scalar multiplications: Sign Change Attacks. These attacks exploit di#erent number representations as they are often employed in modern cryptographic applications. Previously, fault attacks on elliptic curves aimed to force a device to output points which are on a cryptographically weak curve. Such attacks can easily be defended against. Our attack produces points which do not leave the curve and are not easily detected. The paper also presents a revised scalar multiplication algorithm that provably protects against Sign Change Attacks.
Are standards compliant elliptic curve cryptosystems feasible on RFID
 In Proc. of RFIDSec’06
, 2006
"... Abstract. With elliptic curve cryptography emerging as a serious alternative, the desired level of security can be attained with significantly smaller key sizes. This makes ECC very attractive for smallfootprint devices with limited computational capability, memory and lowbandwidth network connect ..."
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Cited by 26 (1 self)
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Abstract. With elliptic curve cryptography emerging as a serious alternative, the desired level of security can be attained with significantly smaller key sizes. This makes ECC very attractive for smallfootprint devices with limited computational capability, memory and lowbandwidth network connections. However ECC is still considered to be impracticable for very lowend constrained devices like sensor networks and RFID tags. We present a standalone highly area optimized ECC processor design for standards compliant binary field curves. We use the fast squarer implementation to construct an addition chain that allows inversion to be computed efficiently. Hence, we propose an affine coordinate ASIC implementation of the ECC processor using a modified Montgomery point multiplication method for binary curves ranging from 113 − 193 bits. An area between 10k and 18k gates on a 0.35um CMOS process is possible for the different curves which makes the design very attractive for enabling ECC in constrained devices. Key Words: Elliptic curve cryptography (ECC), finite fields, Fermat’s little theorem.
Customizable elliptic curve cryptosystems
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2005
"... Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit s ..."
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Cited by 16 (2 self)
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Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets userdefined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster
Authentication of FPGA bitstreams: why and how
 In Applied Reconfigurable Computing, volume 4419 of LNCS
, 2007
"... Abstract. Encryption of volatile FPGA bitstreams provides confidentiality to the design but does not ensure its authenticity. This paper motivates the need for adding authentication to the configuration process by providing application examples where this functionality would be useful. An examinatio ..."
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Cited by 14 (3 self)
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Abstract. Encryption of volatile FPGA bitstreams provides confidentiality to the design but does not ensure its authenticity. This paper motivates the need for adding authentication to the configuration process by providing application examples where this functionality would be useful. An examination of possible solutions is followed by suggesting a practical one in consideration of the FPGA’s configuration environment constraints. The solution proposed here involves two symmetrickey encryption cores running in parallel to provide both authentication and confidentiality while sharing resources for efficient implementation. 1
Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems
 Proceedings of Topics in Cryptology  CTRSA 2004. Lecture Note in Computer Science
, 2004
"... Abstract. This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting w ..."
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Cited by 10 (3 self)
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Abstract. This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless applications, up to a very big design (more than 100 Kgates) used for network security. In latter option it can include a few dedicated large number arithmetic units each of which is a systolic array performing the Montgomery Modular Multiplication (MMM). The bound on the Montgomery parameter has been optimized to facilitate more secure ECC point operations. Furthermore, we present a new possibility for CRT scheme which is less vulnerable to sidechannel attacks.
Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array
"... This paper describes a hardware architecture for modular multiplication operation which is efficient for bitlengths suitable for both commonly used types of Public Key Cryptography (PKC) i.e. ECC and RSA Cryptosystems. The challenge of current PKC implementations is to deal with long numbers (1602 ..."
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Cited by 9 (2 self)
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This paper describes a hardware architecture for modular multiplication operation which is efficient for bitlengths suitable for both commonly used types of Public Key Cryptography (PKC) i.e. ECC and RSA Cryptosystems. The challenge of current PKC implementations is to deal with long numbers (1602048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on the Montgomery's Multiplication Method (MMM).
Efficient Hardware Implementation of Finite Fields with Applications to Cryptography
 ACTA APPL MATH (2006 ) 93 : 75–118
, 2006
"... The paper presents a survey of most common hardware architectures for finite field arithmetic especially suitable for cryptographic applications. We discuss architectures for three types of finite fields and their special versions popularly used in cryptography: binary fields, prime fields and exten ..."
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Cited by 9 (0 self)
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The paper presents a survey of most common hardware architectures for finite field arithmetic especially suitable for cryptographic applications. We discuss architectures for three types of finite fields and their special versions popularly used in cryptography: binary fields, prime fields and extension fields. We summarize algorithms and hardware architectures for finite field multiplication, squaring, addition/subtraction, and inversion for each of these fields. Since implementations in hardware can either focus on highspeed or on areatime efficiency, a careful choice of the appropriate set of architectures has to be made depending on the performance requirements and available area.
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks
"... This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (doubleaddsubtract) is modified so that the processor performs the same operations for every 3 bits of the scalar k independent ..."
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Cited by 6 (0 self)
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This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (doubleaddsubtract) is modified so that the processor performs the same operations for every 3 bits of the scalar k independent of the bit pattern of the 3 bits. Therefore, it is not possible to extract the key pattern using a timing attack. The data flow graph of the modified algorithm is derived and the underlying Galois Field operators are scheduled so that the point multiplication delay is minimized. The architecture of this processor is based on the Galois Field of GF(2 n) and the bitserial field multiplier and squarer are designed. The processor is configurable for any value of n and the delay of point multiplication is [18(n+3) + (n+3)/2 + 1]×(n/3) clock cycles. For the case of GF(2 163) the point multiplication delay is 165888 clock cycles.
A Stateoftheart Elliptic Curve Cryptographic Processor Operating in the Frequency Domain
"... Abstract. We propose a novel area/time efficient ECC processor architecture which performs all finite field arithmetic operations in the discrete Fourier domain. The proposed architecture utilizes a class of Optimal Extension Fields (OEF) GF (q m) where the field characteristic is a Mersenne prime q ..."
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Cited by 5 (1 self)
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Abstract. We propose a novel area/time efficient ECC processor architecture which performs all finite field arithmetic operations in the discrete Fourier domain. The proposed architecture utilizes a class of Optimal Extension Fields (OEF) GF (q m) where the field characteristic is a Mersenne prime q = 2 n − 1 and m = n. The main advantage of our architecture is that it achieves extension field modular multiplication in the discrete Fourier domain with only a linear number of base field GF (q) multiplications in addition to a quadratic number of simpler operations such as addition and bitwise rotation. We achieve an area between 25k and 50k equivalent gates for the implementation of OEFs of size 169, 289 and 361 bits. With its low area and high speed, the proposed architecture is well suited for elliptic curve cryptography in small device environments such as sensor networks. The work at hand presents the first hardware implementation of a frequency domain multiplier suitable for elliptic curve cryptography and the first hardware implementation of ECC in the frequency domain.