Results 21  30
of
45
A Parallel State Assignment Algorithm for Finite State Machines
"... Abstract. This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to overcome the computational complexity involved in the optimization of large sequential circuits. FSMs constitu ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
(Show Context)
Abstract. This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to overcome the computational complexity involved in the optimization of large sequential circuits. FSMs constitute an important class of logic circuits, and state assignment is one of the key steps in combinational logic optimization. The SMPbased parallel algorithm – based on the sequential program JEDI targeting multilevel logic implementation – scales nearly linearly with the number of processors for FSMs of varying problem sizes chosen from standard benchmark suites while attaining quality of results comparable to the best sequential algorithms. 1
FSMs state encoding targeting at logic level minimization
, 2006
"... Abstract. The paper concerns the problem of state assignment for finite state machines (FSM), targeting at PALbased CPLDs implementations. Presented in the paper approach is dedicated to state encoding of fast automata. The main idea is to determine the number of logic levels of the transition func ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
(Show Context)
Abstract. The paper concerns the problem of state assignment for finite state machines (FSM), targeting at PALbased CPLDs implementations. Presented in the paper approach is dedicated to state encoding of fast automata. The main idea is to determine the number of logic levels of the transition function before the state encoding process, and keep the constraints during the process. The number of implicants of every single transition function must be known while assigning states, so elements of two level minimization based on Primary and Secondary Merging Conditions are implemented in the algorithm. The method is based on code length extraction if necessary. In one of the most basic stages of the logic synthesis of sequential devices, the elements referring to constraints of PALbased CPLDs are taken into account.
An Efficient And Effective Approach To ColumnBased Input/Output Encoding In Functional Decomposition
"... Encoding in Curtisstyle decompositions is the process of assigning codes to groups of compatible columns (or cubes) so that the binary logic descriptions of the predecessor and successor subfunctions can be created for further decomposition. In doing so, the subfunctions created are functionally ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
Encoding in Curtisstyle decompositions is the process of assigning codes to groups of compatible columns (or cubes) so that the binary logic descriptions of the predecessor and successor subfunctions can be created for further decomposition. In doing so, the subfunctions created are functionally equivalent to the set of care values specified in the original function. In this paper an input/output encoding algorithm DC ENC is presented that is designed to achieve the simpliest total complexity of the predecessor and successor subfunctions, and to increase the total number of don't cares for their further utilization in subsequent decomposition steps of these subfunctions. 1. Introduction. The Encoding Problem in Functional Decomposition. One of the most promising approaches of modern logic synthesis is general functional decomposition [17, 20, 11]. Together with our collaborators, we developed decomposers TRADE [27], LUTSYN [26] and GUD (all binary), FRED [11, 12] (multivalued f...
Integrated Test of Interacting Controllers and Datapaths
"... This paper is organized as follows. Section 2 presents a system model for testing a datapath/controller pair. Issues central to the testing of controllers are presented in Section 3. These issues include a classification of the types of faults in the controller, and the impact that the controller fa ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
This paper is organized as follows. Section 2 presents a system model for testing a datapath/controller pair. Issues central to the testing of controllers are presented in Section 3. These issues include a classification of the types of faults in the controller, and the impact that the controller faults have on the nonfunctional aspects of the system of manufacturing and power. Section 4 details our solution for integrated datapath/controller testing. Experimental results are shown in Section 5, and concluding remarks are in Section 6.
1An FSM ReEngineering Approach to Sequential Circuit Synthesis by State Splitting
"... We propose Finite State Machine (FSM) reengineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to reconstruct a functionally equivalent but topologically different FSM based on the optimization obj ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
(Show Context)
We propose Finite State Machine (FSM) reengineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to reconstruct a functionally equivalent but topologically different FSM based on the optimization objective, and concludes with another round of FSM synthesis on the reconstructed FSM. This approach explores a larger solution space that consists of a set of FSMs functionally equivalent to the original one, making it possible to obtain better solutions than in the original FSM. Guided by the result from the rst round of synthesis, the solution space exploration process can be rapid and costefcient. We apply this framework to FSM state encoding for power minimization and area minimization. The FSM is rst minimized and encoded using existing state encoding algorithms. Then we develop both a heuristic algorithm and a genetic algorithm to reconstruct the FSM. Finally, the FSM is reencoded by the same encoding algorithms. To demonstrate the effectiveness of this framework, we conduct experiments on MCNC91 sequential circuit benchmarks. The circuits are read in and synthesized in SIS environment. After FSM reengineering are performed, we measure the power, area and delay in the newly synthesized circuits. In the powerdriven synthesis, we observe an average 5.5 % of total power reduction with 1.3 % area increase and 1.3 % delay increase. This results are in general better than other low power state encoding techniques on comparable cases. In the areadriven synthesis, we observe an average 2.7 % area reduction, 1.8% delay reduction, and 0.4 % power increase. Finally, we use integer linear programming to obtain the optimal low power state encoding for benchmarks of small size. We nd that the optimal solutions in the re engineered FSMs are 1 % to 8% better than the optimal solutions in the original FSMs in terms of power minimization. I.
Back to the Roots: Implementing the RTOS as a Specialized State Machine
"... Abstract — Realtime control systems, originally arisen from simple, statemachine–based discrete elements, nowadays comprise sophisticated and manifold softwarebased algorithms consolidated with different applications on single, yet powerful microcontrollers. Realtime operating systems were int ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract — Realtime control systems, originally arisen from simple, statemachine–based discrete elements, nowadays comprise sophisticated and manifold softwarebased algorithms consolidated with different applications on single, yet powerful microcontrollers. Realtime operating systems were introduced to handle this complexity by providing APIs to describe the desired system behavior, however, at the cost of losing the clarity and explicitness of statemachine–based representations. This paper presents an approach to bring the RTOS back to the roots of a hardwareimplementable finite state machine. The concept is based on a detailed static analysis of the application–kernel interaction to distill the realtime operating system behavior and find a FSMbased representation of the expected OS states and transitions. We apply our idea to a realistic control application based on an OSEK operating system, which results in a feasibly sized programmable logic array implementation. Having such a representation at hand might further leverage thorough system verification and validation based on existing and mature FSM analysis tools. I.
Design and Synthesis of SelfCheckmg VLSI Circuits
"... AbstractSelfchecking circuits can detect the presence of both transient and permanent faults. A selfchecking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as wel ..."
Abstract
 Add to MetaCart
AbstractSelfchecking circuits can detect the presence of both transient and permanent faults. A selfchecking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A selfchecking system consists of an interconnection of selfchecking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Although much effort has been concentrated on the design of selfchecking checkers by previous researchers, very few results have been presented for the design of selfchecking functional circuits. In this paper, we explore methods for the costeffective design of combinational and sequential selfchecking functional circuits and checkers. The area overhead for all proposed design alternatives is studied in detail. I.
Design Space . . . in Modern Embedded Systems
"... Power minimization is a critical challenge for modern embedded system design. Recently, due to the rapid increase of system’s complexity and the power density, there is a growing need for power control techniques at various design levels. Meanwhile, due to technology scaling, leakage power has beco ..."
Abstract
 Add to MetaCart
Power minimization is a critical challenge for modern embedded system design. Recently, due to the rapid increase of system’s complexity and the power density, there is a growing need for power control techniques at various design levels. Meanwhile, due to technology scaling, leakage power has become a significant part of power dissipation in the CMOS circuits and new techniques are needed to reduce leakage power. As a result, many new power minimization techniques have been proposed such as voltage island, gate sizing, multiple supply and threshold voltage, power gating and input vector control, etc. These design options further enlarge the design space and make it prohibitively expensive to explore for the most energy efficient design solution. Consequently, heuristic algorithms and randomized algorithms are frequently used to explore the design space, seeking suboptimal solutions to meet the timetomarket requirements. These algorithms are based on the idea of truncating the design space and restricting the search in a subset of the original design space. While this approach can effectively reduce the runtime of searching, it may also
DegreeOfFreedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
"... Abstract This paper reports the design of BIST structures for sequential machines. Testability of an F S M is limited due to the fact that some machine states remain unreachable and some act as a sink under any input sequence. The proposed scheme provides uniform mobility, referred to as degree of ..."
Abstract
 Add to MetaCart
Abstract This paper reports the design of BIST structures for sequential machines. Testability of an F S M is limited due to the fact that some machine states remain unreachable and some act as a sink under any input sequence. The proposed scheme provides uniform mobility, referred to as degree of freedom, among the machine states in test mode by enhancing the reachability and emitability of the states. Uniform mobility of states ensures higher fault e ciency in a BISTstructure. A graph based approach is introduced for state code assignment t o minimize gate area. Experimental results on benchmark circuits establish that the proposed scheme does improve the BISTquality simultaneously reducing the gate area of the synthesized machine.
Logic Synthesis v TABLE OF CONTENTS
, 1991
"... Iwould especially like to thank Steve Levitan for his guidance and patience throughout the development of this tool. ..."
Abstract
 Add to MetaCart
(Show Context)
Iwould especially like to thank Steve Levitan for his guidance and patience throughout the development of this tool.