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Analytical Modeling of High Performance Reconfigurable Computers: Prediction and Analysis of System Performance
, 2002
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Towards a Reconfigurable Nanocomputer Platform
- in Proc. of the 7th Asia-Pacific Computer Systems Architectures Conference (ACSAC
, 2002
"... Some ideas are presented for achieving lowoverhead reconfigurability in systems built from nanoscale components. Via three example circuits, it is demonstrated how it will be possible to exploit a number of alternative "dimensions" -- apart from the obvious spatial dimension - to construct ..."
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Some ideas are presented for achieving lowoverhead reconfigurability in systems built from nanoscale components. Via three example circuits, it is demonstrated how it will be possible to exploit a number of alternative "dimensions" -- apart from the obvious spatial dimension - to construct compact configurable cells. Configurability based on dual gate transistors using RTD-based multi-valued logic and the variable resistance of phase-change films are shown. A high-density non-volatile reconfigurable cell is proposed in which a double junction spin filter tunnel junction is built on a vertical conducting pillar and integrated into a nearest neighbour-connected mesh. Some brief comments are made about how computing applications might exploit such a homogenous non-volatile processing mesh.
by The Co-Design of Virtual Machines Using Reconfigurable Hardware
"... All rights reserved. This dissertation may not be reproduced in whole or in part, by photocopying or other means, without the permission of the author. University of Victoria We accept this dissertation as conforming to the required standard ..."
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All rights reserved. This dissertation may not be reproduced in whole or in part, by photocopying or other means, without the permission of the author. University of Victoria We accept this dissertation as conforming to the required standard
A Low-Power Multiprocessor Architecture for Embedded Reconfigurable Systems
"... In this paper, we introduce the architecture of a new embedded field programmable processor array (E-FPPA) which consists of a low-power multiprocessor system embedded with standard programmable logic blocks and memory. Each block (processor, programmable logic,...) is coupled to a transfer controll ..."
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In this paper, we introduce the architecture of a new embedded field programmable processor array (E-FPPA) which consists of a low-power multiprocessor system embedded with standard programmable logic blocks and memory. Each block (processor, programmable logic,...) is coupled to a transfer controller (TC) responsible of all the transfers between blocks. Instead of using a classical crossbar interconnection network, we propose a low cost hierarchical ring which combines simple interface and high performance communications when data locality is observed. Based on the E-FPPA, high performance reconfigurable systems can be easily built and we demonstrate that this architecture is an interesting alternative to traditional DSP for low-power applications. By using the 8-bit CoolRisc processor [1,2], an E-FPPA including a cluster of 16 processors, 16 TC, working respectively at 25 and 50 MHz, and 1kbytes data SRAM for each processor, consumes 2 W with a peak performance of 1200 Mops. The chip...
The Security Council
- Conflict Studies Research Centre, Essay C94
, 1997
"... This Dissertation is brought to you for free and open access by the Graduate School at Trace: Tennessee Research and Creative Exchange. It has been ..."
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This Dissertation is brought to you for free and open access by the Graduate School at Trace: Tennessee Research and Creative Exchange. It has been
Header for SPIE use Programming High Performance Reconfigurable Computers
"... High Performance Computers (HPC) provide dramatically improved capabilities for a number of defense and commercial applications, but often are too expensive to acquire and to program. The smaller market and customized nature of HPC architectures combine to increase the cost of most such platforms. T ..."
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High Performance Computers (HPC) provide dramatically improved capabilities for a number of defense and commercial applications, but often are too expensive to acquire and to program. The smaller market and customized nature of HPC architectures combine to increase the cost of most such platforms. To address the problems with high hardware costs, one may create more inexpensive Beowolf clusters of dedicated commodity processors. Despite the benefit of reduced hardware costs, programming the HPC platforms to achieve high performance often proves extremely time-consuming and expensive in practice. In recent years, programming productivity gains come from the development of common APIs and libraries of functions to support distributed applications. Examples include PVM, MPI, BLAS, and VSIPL. The implementation of each API or library is optimized for a given platform, but application developers can write code that is portable across specific HPC architectures. The application of reconfigurable computing (RC) into HPC platforms promises significantly enhanced performance and flexibility at a modest cost. Unfortunately, configuring (programming) the reconfigurable computing nodes remains a challenging task and relatively little work to date has focused on potential high performance reconfigurable computing (HPRC) platforms consisting of reconfigurable nodes paired with processing nodes. This paper addresses the challenge of effectively exploiting HPRC resources by first considering the performance evaluation and optimization problem before turning to improving the programming infrastructure used for porting applications to HPRC platforms.
Compilation Increasing the Scheduling Scope for Multi- Memory-FPGA-based Custom Computing Machines ∗
"... Abstract. This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled wit ..."
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Abstract. This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented by an hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied. 1.
Anais do REC07 III Jornadas sobre Sistemas Reconfiguráveis Lisboa, Portugal FPGA Architectures for Reconfigurable Computing
"... To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration ..."
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To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable
The Theoretical Development of a New High Speed
, 2005
"... Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are large, expensive, and still not fast enough to make the Monte Carlo technique useful for calculations requiring a near real-time eval ..."
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Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are large, expensive, and still not fast enough to make the Monte Carlo technique useful for calculations requiring a near real-time evaluation period. For Monte Carlo simulations, a small computational unit called a Field Programmable Gate Array (FPGA) is capable of bringing the power of a large cluster computer into any personal computer (PC). Because an FPGA is capable of executing Monte Carlo simulations with a high degree of parallelism, a simulation run on a large FPGA can be executed at a much higher rate than an equivalent simulation on a modern single-processor desktop PC. In this thesis, a simple radiation transport problem involving moderate energy photons incident on a three-dimensional target is discussed. By comparing the theoretical evaluation speed of this transport problem on a large FPGA to the evaluation speed of the same transport problem using standard computing techniques, it is shown that it is possible to accelerate Monte Carlo computations significantly using FPGAs. In fact, we have found that our simple photon transport test case can be evaluated in excess
JPEG Image compression on MorphoSys: Mapping and Performance Analysis ABSTRACT
"... Information has become an important commodity in the world we live in. But with the build up of information, the need comes to store and transmit this huge amount of data. This is faced with expensive and limited storage devices in addition to limited bandwidth. To solve this problem, the field of d ..."
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Information has become an important commodity in the world we live in. But with the build up of information, the need comes to store and transmit this huge amount of data. This is faced with expensive and limited storage devices in addition to limited bandwidth. To solve this problem, the field of data compression emerged to reduce the size of data and make it easier to store and transmit. There have been many algorithms devised to compress data and a significant part of these algorithms targeted image compression for two reasons, the first is the large size that image files take, the second is the concern for the quality of the image. In this paper we present the MorphoSys Reconfigurable architecture as a system capable of executing data compression algorithms, especially image compression, with very high performance. A mapping of the JPEG image compression algorithm is proposed. A performance analysis study is also presented to evaluate the efficiency of JPEG execution on the MorphoSys system and to compare it with other Reconfigurable, general purpose and ASIC architectures.
