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LDPC block and convolutional codes based on circulant matrices
 IEEE TRANS. INFORM. THEORY
, 2004
"... A class of algebraically structured quasicyclic (QC) lowdensity paritycheck (LDPC) codes and their convolutional counterparts is presented. The QC codes are described by sparse paritycheck matrices comprised of blocks of circulant matrices. The sparse paritycheck representation allows for prac ..."
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Cited by 93 (8 self)
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A class of algebraically structured quasicyclic (QC) lowdensity paritycheck (LDPC) codes and their convolutional counterparts is presented. The QC codes are described by sparse paritycheck matrices comprised of blocks of circulant matrices. The sparse paritycheck representation allows for practical graphbased iterative messagepassing decoding. Based on the algebraic structure, bounds on the girth and minimum distance of the codes are found, and several possible encoding techniques are described. The performance of the QC LDPC block codes compares favorably with that of randomly constructed LDPC codes for short to moderate block lengths. The performance of the LDPC convolutional codes is superior to that of the QC codes on which they are based; this performance is the limiting performance obtained by increasing the circulant size of the base QC code. Finally, a continuous decoding procedure for the LDPC convolutional codes is described.
Error floors of LDPC codes on the binary symmetric channel,” in
 Proc. IEEE Int. Conf. on Commun. (ICC ’06),
, 2006
"... AbstractIn this paper, we propose a semianalytical method to compute error floors of LDPC codes on the binary symmetric channel decoded iteratively using the Gallager B algorithm. The error events of the decoder are characterized using combinatorial objects called trapping sets, originally define ..."
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Cited by 36 (7 self)
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AbstractIn this paper, we propose a semianalytical method to compute error floors of LDPC codes on the binary symmetric channel decoded iteratively using the Gallager B algorithm. The error events of the decoder are characterized using combinatorial objects called trapping sets, originally defined by Richardson. In general, trapping sets are characteristic of the graphical representation of a code. We study the structure of trapping sets and explore their relation to graph parameters such as girth and vertex degrees. Using the proposed method, we compute error floors of regular structured and random LDPC codes with column weight three.
Shortened array codes of large girth
 IEEE TRANSACTIONS ON INFORMATION THEORY
, 2008
"... One approach to designing structured lowdensity paritycheck (LDPC) codes with large girth is to shorten codes with small girth in such a manner that the deleted columns of the paritycheck matrix contain all the variables involved in short cycles. This approach is especially effective if the par ..."
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Cited by 24 (1 self)
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One approach to designing structured lowdensity paritycheck (LDPC) codes with large girth is to shorten codes with small girth in such a manner that the deleted columns of the paritycheck matrix contain all the variables involved in short cycles. This approach is especially effective if the paritycheck matrix of a code is a matrix composed of blocks of circulant permutation matrices, as is the case for the class of codes known as array codes. We show how to shorten array codes by deleting certain columns of their paritycheck matrices so as to increase their girth. The shortening approach is based on the observation that for array codes, and in fact for a slightly more general class of LDPC codes, the cycles in the corresponding Tanner graph are governed by certain homogeneous linear equations with integer coefficients. Consequently, we can selectively eliminate cycles from an array code by only retaining those columns from the paritycheck matrix of the original code that are indexed by integer sequences that do not contain solutions to the equations governing those cycles. We provide Ramseytheoretic estimates for the maximum number of columns that can be retained from the original paritycheck matrix with the property that the sequence of their indices avoid solutions to various types of cyclegoverning equations. This translates to estimates of the rate penalty incurred in shortening a code to eliminate cycles. Simulation results show that for the codes considered, shortening them to increase the girth can lead to significant gains in signaltonoise ratio in the case of communication over an additive white Gaussian noise channel.
Quantum quasicyclic LDPC codes
 In Proc. ISIT’07
, 2007
"... Abstract — In this paper, a construction of a pair of quasicyclic LDPC codes to construct a quantum errorcorrecting code is proposed. Our construction method is based on algebraic combinatrics and have lots of variations for length, code rate. I. ..."
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Cited by 19 (1 self)
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Abstract — In this paper, a construction of a pair of quasicyclic LDPC codes to construct a quantum errorcorrecting code is proposed. Our construction method is based on algebraic combinatrics and have lots of variations for length, code rate. I.
SplitRow: A reduced complexity, high throughput LDPC decoder architecture
 in ICCD
, 2006
"... Abstract — A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed SplitRow method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and sig ..."
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Cited by 18 (9 self)
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Abstract — A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed SplitRow method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors— which results in smaller area, higher speeds, and lower energy dissipation. Simulation results over an additive white Gaussian channel show that the error performance of high rowweight codes with SplitRow decoding is within 0.3–0.6 dB of the MinSum and SumProduct decoding algorithms. A full parallel decoder for a (3,6) LDPC code with a code length of 1536 bits is implemented in a 0.18 µm CMOS technology twice: once using the SplitRow method, and once using the MinSum algorithm for comparison. The SplitRow decoder operates at 53 MHz and delivers a throughput of 5.4 Gbps with 15 decoding iterations per block. The SplitRow decoder is about 1.3 times smaller, has an average wire length 1.5 times shorter, and has a throughput 1.6 times higher than the MinSum decoder. I.
Next generation FEC for highcapacity communication in optical transport networks
 J. LIGHTW. TECHNOL
, 2009
"... Codes on graphs of interest for next generation forward error correction (FEC) in highspeed optical networks, namely turbo codes and lowdensity paritycheck (LDPC) codes, are described in this invited paper. We describe both binary and nonbinary LDPC codes, their design, and decoding. We also disc ..."
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Cited by 16 (4 self)
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Codes on graphs of interest for next generation forward error correction (FEC) in highspeed optical networks, namely turbo codes and lowdensity paritycheck (LDPC) codes, are described in this invited paper. We describe both binary and nonbinary LDPC codes, their design, and decoding. We also discuss an FPGA implementation of decoders for binary LDPC codes. We then explain how to combine multilevel modulation and channel coding optimally by using coded modulation. Also, we describe an LDPCcoded turboequalizer as a candidate for dealing simultaneously with fiber nonlinearities, PMD, and residual chromatic dispersion.
Decomposition methods for large scale LP decoding
 In 49th Annual Allerton Conference on Communication, Control, and Computing
, 2011
"... Abstract When binary linear errorcorrecting codes are used over symmetric channels, a relaxed version of the maximum likelihood decoding problem can be stated as a linear program (LP). This LP decoder can be used to decode at biterrorrates comparable to stateoftheart belief propagation (BP) d ..."
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Cited by 15 (3 self)
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Abstract When binary linear errorcorrecting codes are used over symmetric channels, a relaxed version of the maximum likelihood decoding problem can be stated as a linear program (LP). This LP decoder can be used to decode at biterrorrates comparable to stateoftheart belief propagation (BP) decoders, but with significantly stronger theoretical guarantees. However, LP decoding when implemented with standard LP solvers does not easily scale to the block lengths of modern error correcting codes. In this paper we draw on decomposition methods from optimization theory, specifically the Alternating Directions Method of Multipliers (ADMM), to develop efficient distributed algorithms for LP decoding. The key enabling technical result is a nearly linear time algorithm for twonorm projection onto the parity polytope. This allows us to use LP decoding, with all its theoretical guarantees, to decode largescale error correcting codes efficiently. We present numerical results for two LDPC codes. The first is the rate0.5 [2640, 1320] "Margulis" code, the second a rate0.77 [1057.244] code. The "waterfall" region of LP decoding is seen to initiate at a slightly higher signaltonoise ratio than for sumproduct BP, however an errorfloor is not observed for either code, which is not the case for BP. Our implementation of LP decoding using ADMM executes as quickly as our baseline sumproduct BP decoder, is fully parallelizable, and can be seen to implement a type of messagepassing with a particularly simple schedule.
Highthroughput LDPC decoders using a multiple splitrow method
 in ICASSP, 2007
"... Abstract We propose the "MultiSplitRow " LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed SplitRow decoding method. MultiSplitRow is especially useful for regul ..."
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Cited by 14 (9 self)
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Abstract We propose the "MultiSplitRow " LDPC decoding method which allows further reductions in routing complexity, greater throughput, and smaller circuit area implementations compared to the previously proposed SplitRow decoding method. MultiSplitRow is especially useful for regular high row weight LDPC codes. A 2048bit full parallel decoder is implemented in a 0.18,um CMOS technology using standard MinSum, SplitRow2 and SplitRow4 methods. The SplitRow4 decoder delivers 7.1 Gbps throughput with 15 decoding iterations, and has 3.2 times smaller circuit area and 5.2 times higher throughput than the standard MinSum decoder.
A LowComplexity MessagePassing Algorithm for Reduced Routing Congestion in LDPC Decoders
"... Abstract—A lowcomplexity messagepassing algorithm, called SplitRow Threshold, is used to implement lowdensity paritycheck (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASET standard are implemented using MinSum Normalized and MinSum ..."
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Cited by 12 (3 self)
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Abstract—A lowcomplexity messagepassing algorithm, called SplitRow Threshold, is used to implement lowdensity paritycheck (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASET standard are implemented using MinSum Normalized and MinSum SplitRow Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel =16decoder in 65nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Lowpower operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s—just above the 10GBASET requirement—and an estimated average power of 62 mW, resulting in 9.5 pJ/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8 lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm2 with a final postlayout area utilization of 97%. Index Terms—Full parallel, high throughput, lowdensity parity check (LDPC), low power, message passing, min sum, nanometer, 10GBASET, 65nm CMOS, 802.3an. I.
Design of LDPC Codes: A Survey and New Results
"... Abstract — This survey paper provides fundamentals in the design of LDPC codes. To provide a target for the code designer, we first summarize the EXIT chart technique for determining (near)optimal degree distributions for LDPC code ensembles. We also demonstrate the simplicity of representing codes ..."
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Cited by 12 (2 self)
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Abstract — This survey paper provides fundamentals in the design of LDPC codes. To provide a target for the code designer, we first summarize the EXIT chart technique for determining (near)optimal degree distributions for LDPC code ensembles. We also demonstrate the simplicity of representing codes by protographs and how this naturally leads to quasicyclic LDPC codes. The EXIT chart technique is then extended to the special case of protographbased LDPC codes. Next, we present several design approaches for LDPC codes which incorporate one or more accumulators, including quasicyclic accumulatorbased codes. The second half the paper then surveys several algebraic LDPC code design techniques. First, codes based on finite geometries are discussed and then codes whose designs are based on ReedSolomon codes are covered. The algebraic designs lead to cyclic, quasicyclic, and structured codes. The masking technique for converting regular quasicyclic LDPC codes to irregular codes is also presented. Some of these results and codes have not been presented elsewhere. The paper focuses on the binaryinput AWGN channel (BIAWGNC). However, as discussed in the paper, good BIAWGNC codes tend to be universally good across many channels. Alternatively, the reader may treat this paper as a starting point for extensions to more advanced channels. The paper concludes with a brief discussion of open problems. I.