Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.

In this paper we address the problem of state encoding for synchronous finite state machines. The primary goal is the reduction of switching activity in the state register. At the beginning the state transition graph is transformed into an undirected graph where the edges are labeled with the state transition probabilities. Next a maximumspanning tree of the undirected graph is constructed, and we formulate the state encoding problem as an embedding of the spanning tree into a Boolean hypercube of unknown dimension. At this point a modification of Prim's maximum spanning tree algorithm is presented to limit the dimension of the hypercube for area constraints. Then we propose a polynomial time embedding heuristic, which removes the restriction of previous works, where the number of state bits used for encoding of a k-state FSM was generally limited to dlog 2 ke. Next a more sophisticated embedding algorithm is presented, which takes into account the state transition probabilities not co...

The objective of this paper is to provide lower and upper bounds for the switching activity on the state lines in Finite State Machines (FSMs). Using a Markov chain model for the behavior of the states of the FSM, we derive theoretical bounds for the average Hamming distance on the state lines which are valid irrespective of the state encoding used in the final implementation. Such lower and upper bounds, in addition to providing a target for any state assignment algorithm, can also be used as parameters in a high-level model of power, and thus provide an early indication about the performance limits of the target FSM. Experimental results obtained for the mcnc'91 benchmark suite show that our bounds are tighter than the bounds reported previously by other researchers and can be effectively used in a high-level power estimation framework.

Optimization of huge sequential circuits has become unmanageable in CAD of VLSI due to enormous time and memory requirements. In this paper, we report a parallel algorithm for the state assignment problem for finite state machines. Our algorithm has three significant contributions: It is an asynchronous parallel algorithm portable across different MIMD machines. Time and memory requirements reduce by a factor of P (the number of processors), enabling it to handle large problem sizes which the sequential algorithm fails to handle. The quality of the results for multiprocessor runs remains comparable to the sequential algorithm on which it is based. Index Terms : Encoding Hypercube, State Assignment, Memory Scalabilty, Conflict Resolution. 1 Introduction With the rapid improvement in VLSI technology, circuit design is becoming extremely complex and is placing increasing demands on CAD tools. Parallel processing is becoming an attractive solution to reduce the inordinate amount of time...

Low power design is gaining increasing attention as the market for battery powered portable products expands and as power consumption becomes the stumbling block for further system integration. This paper examines strategies to minimize power consumption of digital circuits by reducing the supply voltage, by using power-conscious design methodologies and tools at the behavioral, logic and circuit levels, and by dynamic power management. The paper highlights some of the more effective and promising approaches for achieving ultra low power VLSI circuits and systems.

Abstract not found

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significant power reductions are possible with techniques based on finite state machine (FSM) decomposition. A serious limitation of previously proposed techniques is that they require the state transition graph (STG) of the FSM to be given or extracted from the circuit. Since the size of the STG can be exponential on the number of registers in the circuit, explicit techniques can only be applied to relatively small sequential circuits. In this paper, we present a new approach to perform FSM decomposition by direct manipulation of the circuit. This way, we do not require the STG, either explicit or implicit, thus further avoiding the limitations imposed by the use of BDDs. Therefore, this technique can be applied to circuits with very large STGs. We provide a set of experimental results that show that power consumption can be substantially reduced, in some cases by more than 70%.

This paper presents Metamorphosis 1 -- a novel technique for optimal state assignment targeting multi-level logic implementations. We present a new formulation and synthesis techniques for the state assignment problem based on controlled retiming and re-encoding of a symbolically represented finite state machine (FSM) represented initially with a one-hot code. Metamorphosis is a new design paradigm that integrates the structural and behavioral design methodologies in a synergistic fashion and leverages the additional degrees of freedom to the synthesis of optimal FSM. The proposed technique differs drastically from previous approaches in that the encoding process is guided directly by the cost function (optimization criterion) rather than speculative estimates of the encoding heuristics on the final design cost. We present efficient encoding algorithms for both unconstrained and bit-constrained encoding problems. Another novel feature of Metamorphosis is that it permits the explora...