Abstract — A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (10 9 multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256×512 array of 3-T chargeconserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated on a face detection task. Index Terms — Adiabatic low-power techniques, resonant clock supply, computational memory, pattern recognition. I.

Abstract—We present a resonant adiabatic mixed-signal 128 256 array processor that achieves the energy efficiency of 1.1 TMACS ( multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 3T NMOS unit cell with a single-wire pitch multiplexed bit/com-pute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance vari-ability maintaining sinusoidal clock oscillations near resonance. Index Terms—Adiabatic, charge-recycling, matrix-vector multi-plication, mixed-signal and charge-mode.