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27
Analysis of techniques to improve protocol processing latency
- In Proceedings of the ACM SIGCOMM 1996 Conference
, 1996
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Maximal and nearmaximal shift register sequences: efficient event counters and easy discrete logarithms
- IEEE Trans. Comput
, 1994
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RISC versus CISC: A Tale of Two Chips
- In Computer Architecture News
, 1997
"... This paper compares an aggressive RISC and CISC implementation built with comparable technology. The two chips are the Alpha * 21164 and the Intel ..."
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This paper compares an aggressive RISC and CISC implementation built with comparable technology. The two chips are the Alpha * 21164 and the Intel
Operating systems portability: 8 bits and beyond
- In: 11th IEEE International Conference on Emerging Technology and Factory Automation, September, Prague
, 2006
"... Embedded software often needs to be ported from one system to another. This may happen for a number of reasons among which are the need for using less expen-sive hardware or the need for extra resources. Applica-tion portability can be achieved through an architecture-independent software/hardware i ..."
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Embedded software often needs to be ported from one system to another. This may happen for a number of reasons among which are the need for using less expen-sive hardware or the need for extra resources. Applica-tion portability can be achieved through an architecture-independent software/hardware interface. This is not a straight-forward task in the realm of embedded systems, since they often have very specific platforms. This work shows how an application-oriented component-based op-erating system was developed to allow system and ap-plication portability. Case studies present two embed-ded applications running in different platforms, showing that application source code is totally free of architecture-dependencies. 1.
Emulation of a Virtual Shared Memory Architecture
- Department of Computer Science, University of Bristol, Bristol
, 1993
"... In designing a multiprocessor architecture, the motivating factors are that the architecture should be general purpose, easier to program and at the same time scalable. The Data Diffusion Machine (DDM) seeks to fulfil such criteria. The DDM provides shared-data access on distributed memory hardware, ..."
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In designing a multiprocessor architecture, the motivating factors are that the architecture should be general purpose, easier to program and at the same time scalable. The Data Diffusion Machine (DDM) seeks to fulfil such criteria. The DDM provides shared-data access on distributed memory hardware, allowing data to freely migrate to processors on demand. The DDM concept was originally proposed in terms of a hierarchy of buses, but has since been elaborated for different interconnects. This thesis presents a link-based realisation of the architecture and a link-based coherence protocol which is central in maintaining coherence of data. The link-based protocol exploits the combining properties of the DDM network to minimise traffic in the DDM hierarchy. The protocol also contains efficient and general support for synchronisation. To evaluate the design and performance of new architectures, trace-driven simulation is often used. This thesis presents a novel prototyping and performance ev...
Strategic Directions in Computer Architecture
- ACM Computing Surveys
, 1996
"... Looking back on the last 30 years, we have seen the remarkable developments in semiconductor technology enabling the implementation of ideas that were previ- ..."
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Looking back on the last 30 years, we have seen the remarkable developments in semiconductor technology enabling the implementation of ideas that were previ-
Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures
"... RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing landscape is significantly different: ..."
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RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing landscape is significantly different: growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA). Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. Thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important, and we seek to answer this question through a detailed measurement based study on real hardware running real applications. We analyze measurements on the ARM Cortex-A8 and Cortex-A9 and Intel Atom and Sandybridge i7 microprocessors over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors ’ performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant. 1.
A tale of two processors: Revisiting the RISC-CISC debate
- In 2009 SPEC Benchmark Workshop
"... Abstract. The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the ..."
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Abstract. The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily implemented in RISC cores. This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations. In a 1991 study between VAX and MIPS, Bhandarkar and Clark showed that after canceling out the code size advantage of CISC and the CPI advantage of RISC, the MIPS processor had an average 2.7x advantage over the studied CISC processor (VAX). A 1997 study on Alpha 21064 and the Intel Pentium Pro still showed 5 % to 200 % advantage for RISC for various SPEC CPU95 programs. A decade later and after introduction of interesting techniques such as fusion of micro-operations in the x86, we set off to compare a recent RISC and a recent CISC processor, the IBM POWER5+ and the Intel Woodcrest. We find that the SPEC CPU2006 programs are divided between those showing an advantage on POWER5+ or Woodcrest, narrowing down the 2.7x advantage to nearly 1.0. Our study points to the fact that if aggressive micro-architectural techniques for ILP and high performance can be carefully applied, a CISC ISA can be implemented to yield similar performance as RISC processors. Another interesting observation is that approximately 40 % of all work done on the Woodcrest is wasteful execution in the mispredicted path. 1