. In block multithreaded processors, instruction dependencies occasionally stall the pipeline for one or more processor cycles. The paper uses a timed Petri net model of a multithreaded multiprocessor to study the inuence of pipeline stalls on the performance of processors. Presented results are obtained by simulation of the net model. 1. Introduction The performance of microprocessors has been steadily improving over the last two decades, doubling every 18 months (the so called Moore's law [8]). Although this trend is expected to continue for the next few years [5], it cannot last too long because the shrinking sizes of basic microelectronic devices are nearing their physical limits. Therefore further improvements in microprocessors ' performance will be obtained by other means. Instruction{level parallelism is arguably the best example of such improvements. Two popular approaches to instruction{level parallelism are known as superscalar and VLIW (very long instruction word) ...

In simulation–based performance evaluation, the simulation time is directly related to the complexity of the simulated systems. Since modern multiprocessor systems contain hundreds and even thousands of processors, simulation of such systems can be quite time–demanding. This paper studies multiprocessor systems with different numbers of processors but with the same utilizations of corresponding components; such systems are called performance equivalent. Performance equivalence can be used to simplify simulation–based performance analysis of complex systems by simulating much simpler systems which are equivalent with respect to performance to the original ones. It is shown that in some cases identifying performance equivalent systems is quite straightforward.