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84
Reconfigurable computing: Architectures and design methods
- IEE Proceedings - Computers and Digital Techniques
, 2005
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A TWO-LEVEL RECONFIGURABLE ARCHITECTURE FOR DIGITAL SIGNAL PROCESSING
"... This paper describes a novel reconfigurable architecture for digital signal processing (DSP). The architecture consists of a two-level array of cells and interconnections. DSP algorithms are divided into 4-bit units and mapped onto the first level of cells. Each cell uses a 4x4 matrix of small eleme ..."
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Cited by 20 (8 self)
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This paper describes a novel reconfigurable architecture for digital signal processing (DSP). The architecture consists of a two-level array of cells and interconnections. DSP algorithms are divided into 4-bit units and mapped onto the first level of cells. Each cell uses a 4x4 matrix of small elements to implement the basic operations required by the algorithm. Cells also contain pipeline latches for increased throughput. The two-level architecture features a simple VLSI implementation that combines the flexibility of memory elements with the performance of domino logic. The first prototype has been fabricated using a modest 0.5-µm CMOS technology. Circuit simulations indicate that the cell achieves a clock frequency of 100 MHz.
Parallel LU Factorization of Sparse Matrices on FPGA-Based Configurable Computing Engines
, 2003
"... Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation- intensive applications. With steady advances in silicon technology, as predic ..."
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Cited by 19 (10 self)
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Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation- intensive applications. With steady advances in silicon technology, as predicted by Moore's Law, FieldProgrammable Gate Array (FPGA) technologies have enabled the implementation of System-On-a-Programmable-Chip (SOPC or SOC) computing platforms, which, in turn, have given a significant boost to the field of configurable computing. It is possible to implement various specialized parallel machines in a single silicon chip. In this paper, we describe our design and implementation of a parallel machine on an SOPC development board, using multiple instances of a soft IP configurable processor; we use this machine for LU factorization. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our approach.
Reconfigurable hardware SAT solvers: a survey of systems
- IEEE Transactions on Computers
, 2004
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Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
- In IEEE International Conference on Application-specific Systems, Architectures and Processors
, 2002
"... The exploration of the design space for heterogeneous reconfigurable Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early sta ..."
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Cited by 14 (0 self)
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The exploration of the design space for heterogeneous reconfigurable Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept. 1.
Security on FPGAs: State of the art implementations and attacks
- ACM. Trans. Embedd. Comput. Syst
, 2004
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A medium-grain reconfigurable cell array for DSP application
- in Proc. 3rd iasted International Conference on Circuits, Signals, and Systems, Cancun
, 2003
"... Digital signal processing (DSP) is an essential component of many applications, including multimedia and communications systems. The recent surge in wireless and mobile computing underscores the need for high-performance low power DSP hardware. Reconfigurable hardware balances these requirements wit ..."
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Cited by 8 (4 self)
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Digital signal processing (DSP) is an essential component of many applications, including multimedia and communications systems. The recent surge in wireless and mobile computing underscores the need for high-performance low power DSP hardware. Reconfigurable hardware balances these requirements with development costs by providing system designers a viable alternative to custom integrated circuits. This paper describes a novel reconfigurable architecture for DSP applications. The device contains an array of medium-grain cells that can perform arithmetic, memory, and control operations. The main features of the architecture are as follows: flexible structures, variable word length, pipeline latches, and error correction. A prototype of the cell is being fabricated in 0.5-µm technology. Circuit simulations indicate that the array achieves a clock frequency of 100 MHz even with this modest technology and a performance comparable to the highest-performance DSP processors today.
Delgado-Frias, “Pipelined multipliers for reconfigurable hardware
- in Proc. 11th Reconfigurable Architectures Workshop
"... Reconfigurable devices used in digital signal processing applications must handle large amounts of data in vector form. Most signal processing algorithms use multiplication extensively; thus, the hardware must support this operation to achieve high performance. However, mapping a multiplier on tradi ..."
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Cited by 7 (5 self)
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Reconfigurable devices used in digital signal processing applications must handle large amounts of data in vector form. Most signal processing algorithms use multiplication extensively; thus, the hardware must support this operation to achieve high performance. However, mapping a multiplier on traditional fine-grain devices produces a complex structure whose performance is limited by the routing overhead. In this paper, we present a novel pipelined multiplier structure suitable for medium-grain and coarse-grain reconfigurable cell arrays. We first implement an unsigned n-bit multiplier using m-bit cells. Then, we show how the same structure can work with two’s-complement data with small changes to the configuration. The structure requires ⎡n/m ⎤ 2 cells, but can execute vector operations in a pipelined fashion. We also discuss the benefits of using a hierarchical design for large multipliers. 1.
Memory Security Management for Reconfigurable Embedded Systems
"... The constrained operating environments of many FPGAbased embedded systems require flexible security that can be configured to minimize the impact on FPGA area and power consumption. In this paper, a security approach for external memory in FPGA-based embedded systems that exploits FPGA configurabili ..."
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Cited by 6 (3 self)
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The constrained operating environments of many FPGAbased embedded systems require flexible security that can be configured to minimize the impact on FPGA area and power consumption. In this paper, a security approach for external memory in FPGA-based embedded systems that exploits FPGA configurability is presented. Our FPGA-based security core provides both confidentiality and integrity for data stored externally to an FPGA which is accessed by a processor on the FPGA chip. The benefits of our security core are demonstrated using four embedded applications implemented on a Stratix II device. Each application requires a collection of tasks with varying memory security requirements. Our security core is used in conjunction with a NIOS II soft processor running the MicroC/OS II operating system. An average memory and energy savings of about 64 % and 16%, respectively, is achieved for the four applications versus a non-configurable, uniform security approach. 1
Hybrid CMOS/Nanodevice Circuits for High Throughput Pattern Matching Applications
"... We propose a class of novel hybrid CMOS/nanodevice circuits for pattern matching applications (e.g. real-time network intrusion detection, network packet routing, DNA sequencing), with the potential for dramatic improvements in throughput, density, and power performance relative to state-of-the-art ..."
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Cited by 6 (2 self)
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We propose a class of novel hybrid CMOS/nanodevice circuits for pattern matching applications (e.g. real-time network intrusion detection, network packet routing, DNA sequencing), with the potential for dramatic improvements in throughput, density, and power performance relative to state-of-the-art designs. The performance advantage of our novel circuits is mainly due to three factors: the implementation of a ternary content addressable memory cell with stackable ultradense resistive switching (“memristive ” or RRAM) devices; three dimensional hybrid CMOS/nanodevice circuitry with an area-distributed interface enabling high communication bandwidth between the memory and CMOS subsystems; and use of a modified CMOL FPGA fabric with low reconfiguration overhead. 1.
