The ability of some configurable logic devices to modify their hardware during operation has long held great potential to increase performance and reduce device cost. However, de-spite many research projects and a decade of research, the dynamic reconfiguration of Field Programmable Gate Arrays (FPGAs) is still very much an art practiced by few. Previous attempts to automate the many low-level details that complicate Run-Time Reconfigurable (RTR) application development suffer severe limitations. The proposed research describes a comprehensive approach to dynamic hardware development, providing a designer with appropriate models for computation, communication, and reconfiguration integrated with a high-level design environment. In this way, many manual and time consuming tasks asso-ciated with partial reconfiguration may be hidden, permitting a designer to focus instead on a design’s behavior. The proposed approach frees reconfigurable applications from de-pendence on an external configuration controller, generating a configuration manager from a high-level description. The proposed design and implementation environment will enable effective benchmarking of the benefits of partial reconfiguration and high level synthesis.

This paper presents an easy procedure to develop a reconfigurable application in a Virtuoso real-time operating system using the visual environment TEV developed at DC/UFSCar. In TEV, applications are built using graphs, where nodes are data structures that compose a parallel program (tasks, signals, resources, mailboxes, etc.), and arrows denote the communication and synchronization operations between the data structures. The information in the graphical model can be complemented with code written by the user. Based on this construction, the source code of the application is automatically generated. This work describes a proposal of the TEV extension with reconfigurable applications, denoting R-TEV, using a reconfigurable functions library. A case study is presented, using three reconfigurable functions, and the results show that the proposal is feasible. 1.

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Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissues, and lead to faster patient recovery. Advanced three-dimensional (3D) image processing is a critical need for navigation during IGIs. However, achieving on-demand performance, as required by IGIs, for these image processing operations using software-only implementations is challenging because of the sheer size of the 3D images, and memory and compute intensive nature of the operations. This dissertation, therefore, is geared toward developing high-performance 3D image processing architectures, which will enable improved intraprocedural visualization and navigation capabilities during IGIs. In this dissertation we present an architecture for real-time implementation of 3D filtering operations that are commonly employed for preprocessing of medical images. This architecture is approximately two orders of magnitude faster thancorresponding software implementations and is capable of processing 3D medical images at their acquisition speeds. Combining complementary information through registration between pre- and intraprocedural images is a fundamental need in the IGI workflow. Intensity-based

Abstract:- In this paper the determination of the optimal word-length of the variables implicated in a noise adaptive canceller based on a gradient lattice-ladder algorithm is presented. Upper and lower bounds from the variables are determined from a set of spoken words. Key-Words: Noise cancellation, speech enhancement, integer arithmetic, data format optimization. 1

Dynamic reconfigurable systems can evolve under various conditions due to changes imposed either by the architecture, or by the applications, or by the environment. In such systems, the design process becomes more sophisticated as all the design decisions have to be optimized in terms of runtime behaviors and values. Runtime mapping exploration allows to explore reconfigurable systems at runtime to optimize task mappings in order to adapt to the changing behavior of the application(s), the architecture, or the environment. Performing such explorations at runtime enables a system to be more efficient in terms of various design constraints such as performance, chip area, power consumption, etc. Towards this goal, in this paper, we present a model that facilitates runtime mapping exploration of reconfigurable architectures. A case study of an MJPEG application shows that the presented model can be used to perform runtime exploration of various functional and non-functional design parameters. 1.

Reconfigurable architectures are becoming increasingly popular among designers. This paper presents a survey of design and implementation methods of reconfigurable architectures. Among basic implementation characteristics, systemlevel architectures are presented. Differences between fine- and coarse-grain development are becoming more important. Current trends in reconfigurable computing are adding more heterogeneous functions to the hardware, using softcore processors and using coarse-grained fabrics.

c t i v it y e p o r t 2009 Table of contents 1. Team.................................................................................... 1

This paper reports the impact of different Nios II hardware and software options for arithmetic operations on its power and energy consumption. These options are evaluated on the Cyclone II and Stratix II FPGA families using a number of benchmark programs. This analysis is part of a more complete study oriented to characterize the power and energy consumption of an embedded processor like the Altera’s Nios II. Results are based on physical measurements and show significant energy savings and higher performance in arithmetic operations when available arithmetic hardware suitable for these operations is included. However when the utilization of resources is taken into account, then setups with less hardware and more software for arithmetic computation can be more efficient. 1

Reconfigurable computing has become an essential part of research in the domain of modern computing paradigms. Reconfigurable computing approach integrates both, the performance and flexibility gaining aspects on a single computing system. The computational performance of such kind of systems is crucially dependant on the configuration overheads caused by configuration management unit. Performance of the configuration management unit greatly accelerates the computational power of reconfigurable computing system. There are a large number of control and management techniques which can be used to improve this technology. This research paper presents a comprehensive analysis of existing performance enhancement methodologies in practice. The paper also point outs the different aspects of configuration management for critical analysis and further optimization.